On 30.4.2018 11:07, Alexander Graf wrote:
>
>
> On 30.04.18 10:43, Michal Simek wrote:
>> On 30.4.2018 09:53, Alexander Graf wrote:
>>>
>>>
>>> On 30.04.18 09:37, Michal Simek wrote:
>>>> Xilinx ZynqMP also contains dual Cortex R5 which can run U-Boot.
>>>> This patch is adding minimal support to get U-Boot boot.
>>>> U-Boot on R5 runs out of DDR with default configuration that's why
>>>> DDR needs to be partitioned if there is something else running on arm64.
>>>> Console is done via Cadence uart driver and the first Cadence Triple
>>>> Timer Counter is used for time.
>>>>
>>>> This configuration with uart1 was tested on zcu100-revC.
>>>>
>>>> U-Boot 2018.05-rc2-00021-gd058a08d907d (Apr 18 2018 - 14:11:27 +0200)
>>>>
>>>> Model: Xilinx ZynqMP R5
>>>> DRAM: 512 MiB
>>>> WARNING: Caches not enabled
>>>> MMC:
>>>> In: serial@ff010000
>>>> Out: serial@ff010000
>>>> Err: serial@ff010000
>>>> Net: Net Initialization Skipped
>>>> No ethernet found.
>>>> ZynqMP r5>
>>>>
>>>> There are two ways how to run this on ZynqMP.
>>>> 1. Run from ZynqMP arm64
>>>> tftpb 20000000 u-boot-r5.elf
>>>> setenv autostart no && bootelf -p 20000000
>>>> cpu 4 disable && cpu 4 release 10000000 lockstep
>>>> or
>>>> cpu 4 disable && cpu 4 release 10000000 split
>>>>
>>>> 2. Load via jtag when directly to R5
>>>>
>>>> Signed-off-by: Michal Simek <michal.si...@xilinx.com>
>>>> ---
>>>>
>>>> Changes in v2:
>>>> - Make this a single patch because core support was handled by Lokesh
>>>> Vulta R5 series. Rebase on the top of this series
>>>> - Add reset_cpu which is not handle by core
>>>> - Add MPU support to enable only 0-512MB and RO for 512MB-2GB
>>>> - Enable cache support
>>>> - Wire MTEST macros but not enable mtest command
>>>>
>>>> Changes compare to RFC
>>>> - Use 500MHz instead of 600MHz
>>>> - Remove fpu compilation flags
>>>> - Split arm-r5 code and platform
>>>>
>
>
> [...]
>
>>>> +/* Serial drivers */
>>>> +/* The following table includes the supported baudrates */
>>>> +#define CONFIG_SYS_BAUDRATE_TABLE \
>>>> + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
>>>> +
>>>> +# define CONFIG_ENV_SIZE (128 << 10)
>>>> +
>>>> +/* Allow to overwrite serial and ethaddr */
>>>> +#define CONFIG_ENV_OVERWRITE
>>>> +
>>>> +/* Boot configuration */
>>>> +#define CONFIG_SYS_LOAD_ADDR 0 /* default? */
>>>> +
>>>> +#define CONFIG_SYS_MAXARGS 32 /* max number of command
>>>> args */
>>>> +
>>>> +#define CONFIG_NR_DRAM_BANKS 1
>>>
>>> Is this enough? I would assume people will want to at least cover TCM
>>> and DDR from within U-Boot.
>>
>> Initial expectation is that R5 will run just from DDR because exception
>> vectors are placed at 0x0. It means it is about how big memory you want
>> to assign to R5. I hardcoded it to 0-512MB which should be enough for start.
>>
>> I didn't test TCM that's why it is not there and can be added later when
>> it is tested properly like with others drivers which are not enabled now.
>
> Works for me, it just means more places people could trip over when
> adding additional regions.
>
> Also keep in mind that while U-Boot may run from DDR, it doesn't mean
> whatever it's booting can't use TCM. And if that something happens to be
> a UEFI binary, that would share its address space with U-Boot.
It is not only about TCM. Also OCM can be used for that purpose or
whatever memory in PL.
Thanks,
Michal
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