On 05/18/2018 04:05 PM, Ley Foon Tan wrote: > Preparation for Stratix 10 enablement. In ARM64, L2 cache controller is > accessed through processor registers. So, add CONFIG_SYS_L2_PL310 switch > conditional build in order this file can by shared across other SOCFPGAs. > > Signed-off-by: Chin Liang See <chin.liang....@intel.com> > Signed-off-by: Ley Foon Tan <ley.foon....@intel.com>
Applied 01..05, thanks -- Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
