On Wed, May 30, 2018 at 07:25:14AM +0300, Baruch Siach wrote: > Hi Maxime, > > On Tue, May 29, 2018 at 06:32:01PM +0200, Maxime Ripard wrote: > > On Tue, May 29, 2018 at 05:43:30PM +0200, Stefan Roese wrote: > > > > On Mon, May 28, 2018 at 11:04:38AM +0200, Stefan Roese wrote: > > > > I went back to the thread a bit, but I couldn't really understand what > > > > the issue was exactly. Do you have a spurious slave with the > > > > controller at the address 0x64? When would it happen? Anytime you for > > > > example probe the i2c bus? > > > > > > On the Marvell platforms (Kirkwood, Armada 38x, possibly others), the > > > SoC has the address 0x64 reserved as its I2C slave address (for other > > > masters). So this address is not available for I2C devices attached > > > to the I2C bus. With this patch (via this debug register), this slave > > > address can be "free'ed" making it available for other I2C devices. > > > > Ok. And that fantom slave can be accessed from the controller itself > > when it's the master, or it's only usable by other masters on the bus? > > > > ie, an i2cdetect running on that bus from that controller would detect > > the slave you were mentionning? If so, then we don't have it on the > > Allwinner SoCs (or it's not enabled by default at least). > > Thanks for testing. > > On Armada 38x SoCs this phantom slave only shows up when the bus rate is > 100KHz. At higher rates this slave doesn't show in i2cdetect output, but it > does interfere with long i2c transfers causing bus lockup.
I've never noticed anything similar on any Allwinner SoC, so I guess you can leave out the sunxi case in your code :) Maxime -- Maxime Ripard, Bootlin (formerly Free Electrons) Embedded Linux and Kernel engineering https://bootlin.com
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