This patch adds a driver for the bus associated with a IHS FPGA.
Reviewed-by: Simon Glass <s...@chromium.org>
Signed-off-by: Mario Six <mario....@gdsys.cc>
---
v3 -> v4:
No changes
v2 -> v3:
* Fixed style violations
* Added bindings file
* Added more debug output in case of errors
* Switched all printfs to debug
* Documented the private data structure
* Formatted documentation as proper kernel-doc
* Expanded Kconfig description
v1 -> v2:
* Switched to correct uclass for IHS FPGA driver (now in MISC uclass)
---
.../devicetree/bindings/misc/gdsys,soc.txt | 16 +++++
drivers/misc/Kconfig | 9 +++
drivers/misc/Makefile | 1 +
drivers/misc/gdsys_soc.c | 74 ++++++++++++++++++++++
drivers/misc/gdsys_soc.h | 23 +++++++
5 files changed, 123 insertions(+)
create mode 100644 Documentation/devicetree/bindings/misc/gdsys,soc.txt
create mode 100644 drivers/misc/gdsys_soc.c
create mode 100644 drivers/misc/gdsys_soc.h
diff --git a/Documentation/devicetree/bindings/misc/gdsys,soc.txt
b/Documentation/devicetree/bindings/misc/gdsys,soc.txt
new file mode 100644
index 00000000000..278e935b166
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/gdsys,soc.txt
@@ -0,0 +1,16 @@
+gdsys soc bus driver
+
+This driver provides a simple interface for the busses associated with gdsys
+IHS FPGAs. The bus itself contains devices whose register maps are contained
+within the FPGA's register space.
+
+Required properties:
+- fpga: A phandle to the controlling IHS FPGA
+
+Example:
+
+FPGA0BUS: fpga0bus {
+ compatible = "gdsys,soc";
+ ranges = <0x0 0xe0600000 0x00004000>;
+ fpga = <&FPGA0>;
+};
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 89854a4941b..535be1491e3 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -289,4 +289,13 @@ config GDSYS_IOEP
depends on MISC
help
Support gdsys FPGA's IO endpoint driver.
+
+config GDSYS_SOC
+ bool "Enable gdsys SOC driver"
+ depends on MISC
+ help
+ Support for gdsys IHS SOC, a simple bus associated with each gdsys
+ IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
+ register maps are contained within the FPGA's register map.
+
endmenu
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 3ab110a1aaa..b1f9ce7ed39 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o
obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o
obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o
+obj-$(CONFIG_GDSYS_SOC) += gdsys_soc.o
obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o
obj-$(CONFIG_LED_STATUS) += status_led.o
obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o
diff --git a/drivers/misc/gdsys_soc.c b/drivers/misc/gdsys_soc.c
new file mode 100644
index 00000000000..94a21e08af7
--- /dev/null
+++ b/drivers/misc/gdsys_soc.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2017
+ * Mario Six, Guntermann & Drunck GmbH, mario....@gdsys.cc
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/lists.h>
+
+#include "gdsys_soc.h"
+
+/**
+ * struct gdsys_soc_priv - Private data for gdsys soc bus
+ * @fpga: The gdsys IHS FPGA this bus is associated with
+ */
+struct gdsys_soc_priv {
+ struct udevice *fpga;
+};
+
+static const struct udevice_id gdsys_soc_ids[] = {
+ { .compatible = "gdsys,soc" },
+ { /* sentinel */ }
+};
+
+int gdsys_soc_get_fpga(struct udevice *child, struct udevice **fpga)
+{
+ struct gdsys_soc_priv *bus_priv;
+
+ if (!child->parent) {
+ debug("%s: Invalid parent\n", child->name);
+ return -EINVAL;
+ }
+
+ if (!device_is_compatible(child->parent, "gdsys,soc")) {
+ debug("%s: Not child of a gdsys soc\n", child->name);
+ return -EINVAL;
+ }
+
+ bus_priv = dev_get_priv(child->parent);
+
+ *fpga = bus_priv->fpga;
+
+ return 0;
+}
+
+static int gdsys_soc_probe(struct udevice *dev)
+{
+ struct gdsys_soc_priv *priv = dev_get_priv(dev);
+ struct udevice *fpga;
+ int res = uclass_get_device_by_phandle(UCLASS_MISC, dev, "fpga",
+ &fpga);
+ if (res == -ENOENT) {
+ debug("%s: Could not find 'fpga' phandle\n", dev->name);
+ return -EINVAL;
+ }
+
+ if (res == -ENODEV) {
+ debug("%s: Could not get FPGA device\n", dev->name);
+ return -EINVAL;
+ }
+
+ priv->fpga = fpga;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(gdsys_soc_bus) = {
+ .name = "gdsys_soc_bus",
+ .id = UCLASS_SIMPLE_BUS,
+ .of_match = gdsys_soc_ids,
+ .probe = gdsys_soc_probe,
+ .priv_auto_alloc_size = sizeof(struct gdsys_soc_priv),
+};
diff --git a/drivers/misc/gdsys_soc.h b/drivers/misc/gdsys_soc.h
new file mode 100644
index 00000000000..088d3b65234
--- /dev/null
+++ b/drivers/misc/gdsys_soc.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017
+ * Mario Six, Guntermann & Drunck GmbH, mario....@gdsys.cc
+ */
+
+#ifndef _GDSYS_SOC_H_
+#define _GDSYS_SOC_H_
+
+/**
+ * gdsys_soc_get_fpga() - Retrieve pointer to parent bus' FPGA device
+ * @child: The child device on the FPGA bus needing access to the FPGA.
+ * @fpga: Pointer to the retrieved FPGA device.
+ *
+ * To access their register maps, devices on gdsys soc buses usually have
+ * facilitate the accessor function of the IHS FPGA their parent bus is
+ * attached to. To access the FPGA device from within the bus' children, this
+ * function returns a pointer to it.
+ *
+ * Return: 0 on success, -ve on failure
+ */
+int gdsys_soc_get_fpga(struct udevice *child, struct udevice **fpga);
+#endif /* _GDSYS_SOC_H_ */
--
2.11.0
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