Am Fr., 10. Aug. 2018 um 11:37 Uhr schrieb Bin Meng <bmeng...@gmail.com>: > > Currently building U-Boot as the coreboot payload requires user > to change the build configuration for a specific board during > menuconfig process. This uses the board's native device tree > to configure the hardware. For example, the device tree provides > PCI address range for the PCI host controller and U-Boot will > re-program all PCI devices' BAR to be within this range. In order > to make sure we don't mess up the hardware, we should guarantee > the range matches what coreboot programs the chipset. > > But we really should make the coreboot payload support easier. > Just like EFI payload, we can create a generic coreboot payload > for all x86 boards as well. The payload is configured to include > as many generic drivers as possible. All stuff that touches low > level initialization are not allowed as such is the coreboot's > responsibility. Platform specific drivers (like gpio, spi, etc) > are not included. > > Signed-off-by: Bin Meng <bmeng...@gmail.com>
I really love this generic coreboot payload thing and should simplify the stuff I am working on ( - a generic coreboot payload with some boot logic stuff in it). Reviewed-by: Christian Gmeiner <christian.gmei...@gmail.com> > --- > > arch/x86/cpu/coreboot/Kconfig | 20 +++++------ > arch/x86/cpu/coreboot/coreboot.c | 9 +++-- > arch/x86/dts/Makefile | 1 + > arch/x86/dts/coreboot.dts | 41 > ++++++++++++++++++++++ > board/coreboot/coreboot/Kconfig | 28 +++------------ > board/coreboot/coreboot/Makefile | 2 +- > board/coreboot/coreboot/coreboot.c | 17 +++++++++ > .../coreboot/{coreboot_start.S => start.S} | 0 > configs/coreboot_defconfig | 18 ++++------ > doc/README.x86 | 15 -------- > include/configs/coreboot.h | 32 +++++++++++++++++ > 11 files changed, 116 insertions(+), 67 deletions(-) > create mode 100644 arch/x86/dts/coreboot.dts > create mode 100644 board/coreboot/coreboot/coreboot.c > rename board/coreboot/coreboot/{coreboot_start.S => start.S} (100%) > create mode 100644 include/configs/coreboot.h > > diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig > index 392c258..93f61f2 100644 > --- a/arch/x86/cpu/coreboot/Kconfig > +++ b/arch/x86/cpu/coreboot/Kconfig > @@ -3,26 +3,26 @@ if TARGET_COREBOOT > config SYS_COREBOOT > bool > default y > + imply SYS_NS16550 > + imply SCSI > + imply SCSI_AHCI > imply AHCI_PCI > - imply E1000 > - imply ICH_SPI > imply MMC > imply MMC_PCI > imply MMC_SDHCI > imply MMC_SDHCI_SDMA > - imply SCSI > - imply SCSI_AHCI > - imply SPI_FLASH > - imply SYS_NS16550 > imply USB > imply USB_EHCI_HCD > imply USB_XHCI_HCD > + imply USB_STORAGE > + imply USB_KEYBOARD > imply VIDEO_COREBOOT > + imply E1000 > + imply ETH_DESIGNWARE > + imply PCH_GBE > + imply RTL8169 > imply CMD_CBFS > imply FS_CBFS > - > -config CBMEM_CONSOLE > - bool > - default y > + imply CBMEM_CONSOLE > > endif > diff --git a/arch/x86/cpu/coreboot/coreboot.c > b/arch/x86/cpu/coreboot/coreboot.c > index 69025c1..a6fd3a8 100644 > --- a/arch/x86/cpu/coreboot/coreboot.c > +++ b/arch/x86/cpu/coreboot/coreboot.c > @@ -7,6 +7,7 @@ > > #include <common.h> > #include <fdtdec.h> > +#include <usb.h> > #include <asm/io.h> > #include <asm/msr.h> > #include <asm/mtrr.h> > @@ -75,12 +76,10 @@ int last_stage_init(void) > if (gd->flags & GD_FLG_COLD_BOOT) > timestamp_add_to_bootstage(); > > - board_final_cleanup(); > + /* start usb so that usb keyboard can be used as input device */ > + usb_init(); > > - return 0; > -} > + board_final_cleanup(); > > -int misc_init_r(void) > -{ > return 0; > } > diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile > index 37e4fdc..c62540f 100644 > --- a/arch/x86/dts/Makefile > +++ b/arch/x86/dts/Makefile > @@ -6,6 +6,7 @@ dtb-y += bayleybay.dtb \ > chromebox_panther.dtb \ > chromebook_samus.dtb \ > conga-qeval20-qa3-e3845.dtb \ > + coreboot.dtb \ > cougarcanyon2.dtb \ > crownbay.dtb \ > dfi-bt700-q7x-151.dtb \ > diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts > new file mode 100644 > index 0000000..a94f781 > --- /dev/null > +++ b/arch/x86/dts/coreboot.dts > @@ -0,0 +1,41 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2018, Bin Meng <bmeng...@gmail.com> > + * > + * Generic coreboot payload device tree for x86 targets > + */ > + > +/dts-v1/; > + > +/include/ "skeleton.dtsi" > +/include/ "serial.dtsi" > +/include/ "keyboard.dtsi" > +/include/ "reset.dtsi" > +/include/ "rtc.dtsi" > +/include/ "tsc_timer.dtsi" > + > +/ { > + model = "coreboot x86 payload"; > + compatible = "coreboot,x86-payload"; > + > + aliases { > + serial0 = &serial; > + }; > + > + config { > + silent_console = <0>; > + }; > + > + chosen { > + stdout-path = "/serial"; > + }; > + > + pci { > + compatible = "pci-x86"; > + u-boot,dm-pre-reloc; > + }; > + > + coreboot-fb { > + compatible = "coreboot-fb"; > + }; > +}; > diff --git a/board/coreboot/coreboot/Kconfig b/board/coreboot/coreboot/Kconfig > index cfa1d50..5bd6465 100644 > --- a/board/coreboot/coreboot/Kconfig > +++ b/board/coreboot/coreboot/Kconfig > @@ -9,35 +9,15 @@ config SYS_VENDOR > config SYS_SOC > default "coreboot" > > +config SYS_CONFIG_NAME > + default "coreboot" > + > config SYS_TEXT_BASE > default 0x01110000 > > config BOARD_SPECIFIC_OPTIONS # dummy > def_bool y > - imply SPI_FLASH_ATMEL > - imply SPI_FLASH_EON > - imply SPI_FLASH_GIGADEVICE > - imply SPI_FLASH_MACRONIX > - imply SPI_FLASH_SPANSION > - imply SPI_FLASH_STMICRO > - imply SPI_FLASH_SST > - imply SPI_FLASH_WINBOND > - > -comment "coreboot-specific options" > - > -config SYS_CONFIG_NAME > - string "Board configuration file" > - default "qemu-x86" > - help > - This option selects the board configuration file in include/configs/ > - directory to be used to build U-Boot for coreboot. > - > -config DEFAULT_DEVICE_TREE > - string "Board Device Tree Source (dts) file" > - default "qemu-x86_i440fx" > - help > - This option selects the board Device Tree Source (dts) file in > - arch/x86/dts/ directory to be used to build U-Boot for coreboot. > + select BOARD_EARLY_INIT_R > > config SYS_CAR_ADDR > hex "Board specific Cache-As-RAM (CAR) address" > diff --git a/board/coreboot/coreboot/Makefile > b/board/coreboot/coreboot/Makefile > index ea0f3ee..8db7cc6 100644 > --- a/board/coreboot/coreboot/Makefile > +++ b/board/coreboot/coreboot/Makefile > @@ -10,4 +10,4 @@ > # (C) Copyright 2002 > # Daniel Engström, Omicron Ceti AB, dan...@omicron.se. > > -obj-y += coreboot_start.o > +obj-y += start.o coreboot.o > diff --git a/board/coreboot/coreboot/coreboot.c > b/board/coreboot/coreboot/coreboot.c > new file mode 100644 > index 0000000..ed5606d > --- /dev/null > +++ b/board/coreboot/coreboot/coreboot.c > @@ -0,0 +1,17 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2018, Bin Meng <bmeng...@gmail.com> > + */ > + > +#include <common.h> > + > +int board_early_init_r(void) > +{ > + /* > + * Make sure PCI bus is enumerated so that peripherals on the PCI bus > + * can be discovered by their drivers > + */ > + pci_init(); > + > + return 0; > +} > diff --git a/board/coreboot/coreboot/coreboot_start.S > b/board/coreboot/coreboot/start.S > similarity index 100% > rename from board/coreboot/coreboot/coreboot_start.S > rename to board/coreboot/coreboot/start.S > diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig > index 6af2f23..350acfb 100644 > --- a/configs/coreboot_defconfig > +++ b/configs/coreboot_defconfig > @@ -3,28 +3,25 @@ CONFIG_SYS_TEXT_BASE=0x1110000 > CONFIG_VENDOR_COREBOOT=y > CONFIG_TARGET_COREBOOT=y > CONFIG_FIT=y > -CONFIG_BOOTSTAGE=y > -CONFIG_BOOTSTAGE_REPORT=y > +CONFIG_FIT_SIGNATURE=y > CONFIG_USE_BOOTARGS=y > CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" > +CONFIG_PRE_CONSOLE_BUFFER=y > +CONFIG_PRE_CON_BUF_ADDR=0x100000 > CONFIG_SYS_CONSOLE_INFO_QUIET=y > CONFIG_DISPLAY_BOARDINFO_LATE=y > CONFIG_LAST_STAGE_INIT=y > CONFIG_HUSH_PARSER=y > # CONFIG_CMD_FLASH is not set > CONFIG_CMD_IDE=y > +CONFIG_CMD_MMC=y > CONFIG_CMD_PART=y > -CONFIG_CMD_SF=y > -CONFIG_CMD_SPI=y > CONFIG_CMD_USB=y > # CONFIG_CMD_SETEXPR is not set > CONFIG_CMD_DHCP=y > # CONFIG_CMD_NFS is not set > CONFIG_CMD_PING=y > CONFIG_CMD_TIME=y > -CONFIG_CMD_BOOTSTAGE=y > -CONFIG_CMD_TPM=y > -CONFIG_CMD_TPM_TEST=y > CONFIG_CMD_EXT2=y > CONFIG_CMD_EXT4=y > CONFIG_CMD_EXT4_WRITE=y > @@ -33,11 +30,8 @@ CONFIG_CMD_FS_GENERIC=y > CONFIG_MAC_PARTITION=y > CONFIG_ISO_PARTITION=y > CONFIG_EFI_PARTITION=y > +CONFIG_DEFAULT_DEVICE_TREE="coreboot" > CONFIG_REGMAP=y > CONFIG_SYSCON=y > -CONFIG_SPI=y > -CONFIG_TPM_TIS_LPC=y > -CONFIG_USB_STORAGE=y > -CONFIG_USB_KEYBOARD=y > +# CONFIG_PCI_PNP is not set > CONFIG_CONSOLE_SCROLL_LINES=5 > -CONFIG_TPM=y > diff --git a/doc/README.x86 b/doc/README.x86 > index 9162ea1..6015ca4 100644 > --- a/doc/README.x86 > +++ b/doc/README.x86 > @@ -47,21 +47,6 @@ on other architectures, like below: > $ make coreboot_defconfig > $ make all > > -Note this default configuration will build a U-Boot payload for the QEMU > board. > -To build a coreboot payload against another board, you can change the build > -configuration during the 'make menuconfig' process. > - > -x86 architecture ---> > - ... > - (qemu-x86) Board configuration file > - (qemu-x86_i440fx) Board Device Tree Source (dts) file > - (0x01920000) Board specific Cache-As-RAM (CAR) address > - (0x4000) Board specific Cache-As-RAM (CAR) size > - > -Change the 'Board configuration file' and 'Board Device Tree Source (dts) > file' > -to point to a new board. You can also change the Cache-As-RAM (CAR) related > -settings here if the default values do not fit your new board. > - > Build Instructions for U-Boot as main bootloader > ------------------------------------------------ > > diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h > new file mode 100644 > index 0000000..1cf5c03 > --- /dev/null > +++ b/include/configs/coreboot.h > @@ -0,0 +1,32 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * Copyright (C) 2018, Bin Meng <bmeng...@gmail.com> > + */ > + > +/* > + * board/config.h - configuration options, board specific > + */ > + > +#ifndef __CONFIG_H > +#define __CONFIG_H > + > +#include <configs/x86-common.h> > + > +#define CONFIG_SYS_MONITOR_LEN (1 << 20) > + > +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ > + "stdout=serial,vidconsole\0" \ > + "stderr=serial,vidconsole\0" > + > +/* ATA/IDE support */ > +#define CONFIG_SYS_IDE_MAXBUS 2 > +#define CONFIG_SYS_IDE_MAXDEVICE 4 > +#define CONFIG_SYS_ATA_BASE_ADDR 0 > +#define CONFIG_SYS_ATA_DATA_OFFSET 0 > +#define CONFIG_SYS_ATA_REG_OFFSET 0 > +#define CONFIG_SYS_ATA_ALT_OFFSET 0 > +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0 > +#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170 > +#define CONFIG_ATAPI > + > +#endif /* __CONFIG_H */ > -- > 2.7.4 > > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot -- greets -- Christian Gmeiner, MSc https://christian-gmeiner.info _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot