Add the new board PM9G45 from Ronetix GmbH.
* AT91SAM9G45 MCU at 400Mhz.
* 128MB DDR2 SDRAM
* 256MB NAND
* 4MB DataFlash (optional)
* 10/100 MBits Ethernet DP83848
* Serial number chip DS2401
The board is made as SODIMM200 module.
For more info www.ronatix.at or i...@ronetix.at.
Signed-off-by: Asen Dimov <di...@ronetix.at>
---
MAINTAINERS | 1 +
MAKEALL | 1 +
Makefile | 4 +
board/ronetix/pm9g45/Makefile | 54 ++++
.../at91sam9m10g45ek => ronetix/pm9g45}/config.mk | 0
board/ronetix/pm9g45/pm9g45.c | 317 ++++++++++++++++++++
include/configs/pm9g45.h | 218 ++++++++++++++
7 files changed, 595 insertions(+), 0 deletions(-)
create mode 100644 board/ronetix/pm9g45/Makefile
copy board/{atmel/at91sam9m10g45ek => ronetix/pm9g45}/config.mk (100%)
create mode 100644 board/ronetix/pm9g45/pm9g45.c
create mode 100644 include/configs/pm9g45.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 80057ce..3659947 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -225,6 +225,7 @@ Ilko Iliev <il...@ronetix.at>
PM9261 AT91SAM9261
PM9263 AT91SAM9263
+ PM9G45 ARM926EJS (AT91SAM9G45 SoC)
Gary Jennejohn <ga...@denx.de>
diff --git a/MAKEALL b/MAKEALL
index beacb5f..ad591d5 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -673,6 +673,7 @@ LIST_at91=" \
otc570 \
pm9261 \
pm9263 \
+ pm9g45 \
SBC35_A9G20 \
TNY_A9260 \
TNY_A9G20 \
diff --git a/Makefile b/Makefile
index d801e25..438580a 100644
--- a/Makefile
+++ b/Makefile
@@ -2882,6 +2882,10 @@ otc570_config : unconfig
pm9263_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs pm9263 ronetix at91
+pm9g45_config : unconfig
+ @mkdir -p $(obj)include
+ @$(MKCONFIG) -a pm9g45 arm arm926ejs pm9g45 ronetix at91
+
SBC35_A9G20_NANDFLASH_config \
SBC35_A9G20_EEPROM_config \
SBC35_A9G20_config : unconfig
diff --git a/board/ronetix/pm9g45/Makefile b/board/ronetix/pm9g45/Makefile
new file mode 100644
index 0000000..dd5b02e
--- /dev/null
+++ b/board/ronetix/pm9g45/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian....@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y += pm9g45.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/atmel/at91sam9m10g45ek/config.mk
b/board/ronetix/pm9g45/config.mk
similarity index 100%
copy from board/atmel/at91sam9m10g45ek/config.mk
copy to board/ronetix/pm9g45/config.mk
diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c
new file mode 100644
index 0000000..28221ec
--- /dev/null
+++ b/board/ronetix/pm9g45/pm9g45.c
@@ -0,0 +1,317 @@
+/*
+ * (C) Copyright 2010
+ * Ilko Iliev <il...@ronetix.at>
+ * Asen Dimov <di...@ronetix.at>
+ * Ronetix GmbH <www.ronetix.at>
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian....@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/sizes.h>
+#include <asm/arch/at91sam9g45.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
+#ifdef CONFIG_LCD
+#include <lcd.h>
+#include <atmel_lcdc.h>
+#endif
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+#include <dataflash.h>
+#endif
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_HAS_DATAFLASH
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+ {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+ {0x00000000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "DataFlash"},
+};
+#endif
+
+#ifdef CONFIG_CMD_NAND
+static void pm9g45_nand_hw_init(void)
+{
+ unsigned long csa;
+ at91_smc_t *smc = (at91_smc_t *) AT91_SMC_BASE;
+ at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ /* Enable CS3 */
+ csa = readl(&matrix->ccr[6]) | AT91_MATRIX_CSA_EBI_CS3A;
+ writel(csa, &matrix->ccr[6]);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+
+ writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
+ &smc->cs[3].pulse);
+
+ writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
+ &smc->cs[3].cycle);
+
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ AT91_SMC_MODE_DBW_8 |
+ AT91_SMC_MODE_TDF_CYCLE(3),
+ &smc->cs[3].mode);
+
+ writel(1 << AT91SAM9G45_ID_PIOC, &pmc->pcer);
+
+#ifdef CONFIG_SYS_NAND_READY_PIN
+ /* Configure RDY/BSY */
+ at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+#endif
+
+ /* Enable NandFlash */
+ at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void pm9g45_macb_hw_init(void)
+{
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
+
+ /*
+ * PD2 enables the 50MHz oscillator for Ethernet PHY
+ * 1 - enable
+ * 0 - disable
+ */
+ at91_set_pio_output(AT91_PIO_PORTD, 2, 1);
+ at91_set_pio_value(AT91_PIO_PORTD, 2, 1); /* 1- enable, 0 - disable */
+
+ /* Enable clock */
+ writel(1 << AT91SAM9G45_ID_EMAC, &pmc->pcer);
+
+ /*
+ * Disable pull-up on:
+ * RXDV (PA15) => PHY normal mode (not Test mode)
+ * ERX0 (PA12) => PHY ADDR0
+ * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
+ *
+ * PHY has internal pull-down
+ */
+ writel(1 << 15, &pio->pioa.pudr);
+ writel((1 << 12) | (1 << 13), &pio->pioa.pudr);
+
+ /* Re-enable pull-up */
+ writel(1 << 15, &pio->pioa.puer);
+ writel((1 << 12) | (1 << 13), &pio->pioa.puer);
+
+ at91_macb_hw_init();
+}
+#endif
+
+#ifdef CONFIG_LCD
+void lcd_enable(void)
+{
+ at91_set_a_periph(AT91_PIO_PORTE, 6, 1); /* power up */
+}
+
+void lcd_disable(void)
+{
+ at91_set_a_periph(AT91_PIO_PORTE, 6, 0); /* power down */
+}
+
+static void pm9g45_lcd_hw_init(void)
+{
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTE, 0, 0); /* LCDDPWR */
+ at91_set_a_periph(AT91_PIO_PORTE, 2, 0); /* LCDCC */
+ at91_set_a_periph(AT91_PIO_PORTE, 3, 0); /* LCDVSYNC */
+ at91_set_a_periph(AT91_PIO_PORTE, 4, 0); /* LCDHSYNC */
+ at91_set_a_periph(AT91_PIO_PORTE, 5, 0); /* LCDDOTCK */
+
+ at91_set_a_periph(AT91_PIO_PORTE, 7, 0); /* LCDD0 */
+ at91_set_a_periph(AT91_PIO_PORTE, 8, 0); /* LCDD1 */
+ at91_set_a_periph(AT91_PIO_PORTE, 9, 0); /* LCDD2 */
+ at91_set_a_periph(AT91_PIO_PORTE, 10, 0); /* LCDD3 */
+ at91_set_a_periph(AT91_PIO_PORTE, 11, 0); /* LCDD4 */
+ at91_set_a_periph(AT91_PIO_PORTE, 12, 0); /* LCDD5 */
+ at91_set_a_periph(AT91_PIO_PORTE, 13, 0); /* LCDD6 */
+ at91_set_a_periph(AT91_PIO_PORTE, 14, 0); /* LCDD7 */
+ at91_set_a_periph(AT91_PIO_PORTE, 15, 0); /* LCDD8 */
+ at91_set_a_periph(AT91_PIO_PORTE, 16, 0); /* LCDD9 */
+ at91_set_a_periph(AT91_PIO_PORTE, 17, 0); /* LCDD10 */
+ at91_set_a_periph(AT91_PIO_PORTE, 18, 0); /* LCDD11 */
+ at91_set_a_periph(AT91_PIO_PORTE, 19, 0); /* LCDD12 */
+ at91_set_b_periph(AT91_PIO_PORTE, 20, 0); /* LCDD13 */
+ at91_set_a_periph(AT91_PIO_PORTE, 21, 0); /* LCDD14 */
+ at91_set_a_periph(AT91_PIO_PORTE, 22, 0); /* LCDD15 */
+ at91_set_a_periph(AT91_PIO_PORTE, 23, 0); /* LCDD16 */
+ at91_set_a_periph(AT91_PIO_PORTE, 24, 0); /* LCDD17 */
+ at91_set_a_periph(AT91_PIO_PORTE, 25, 0); /* LCDD18 */
+ at91_set_a_periph(AT91_PIO_PORTE, 26, 0); /* LCDD19 */
+ at91_set_a_periph(AT91_PIO_PORTE, 27, 0); /* LCDD20 */
+ at91_set_b_periph(AT91_PIO_PORTE, 28, 0); /* LCDD21 */
+ at91_set_a_periph(AT91_PIO_PORTE, 29, 0); /* LCDD22 */
+ at91_set_a_periph(AT91_PIO_PORTE, 30, 0); /* LCDD23 */
+
+ writel(1 << AT91SAM9G45_ID_LCDC, &pmc->pcer);
+
+ gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
+}
+
+#ifdef CONFIG_LCD_INFO
+
+void lcd_show_board_info(void)
+{
+ ulong dram_size, nand_size;
+#ifdef CONFIG_HAS_DATAFLASH
+ ulong dataflash_size;
+#endif
+ int i;
+ char temp[32];
+
+ lcd_printf ("%s\n", U_BOOT_VERSION);
+ lcd_printf ("(C) 2010 Ronetix GmbH\n");
+ lcd_printf ("supp...@ronetix.at\n");
+ lcd_printf ("%s CPU at %s MHz\n",
+ CONFIG_SYS_AT91_CPU_NAME,
+ strmhz(temp, get_cpu_clk_rate()));
+
+ dram_size = 0;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+ dram_size += gd->bd->bi_dram[i].size;
+
+ nand_size = 0;
+ for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+ nand_size += nand_info[i].size;
+
+#ifdef CONFIG_HAS_DATAFLASH
+ dataflash_size = 0;
+ for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++) {
+ dataflash_size += (unsigned int)
+ dataflash_info[i].Device.pages_number *
+ dataflash_info[i].Device.pages_size;
+ }
+#endif
+
+ lcd_printf ("%ld MB DDR2 SDRAM\n%ld MB NAND\n",
+ dram_size >> 20,
+ nand_size >> 20);
+
+#ifdef CONFIG_HAS_DATAFLASH
+ lcd_printf ("%ld MB DataFlash\n",
+ dataflash_size >> 20);
+#endif
+}
+#endif /* CONFIG_LCD_INFO */
+#endif
+
+int board_init(void)
+{
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ /* Enable Ctrlc */
+ console_init_f();
+
+ writel((1 << AT91SAM9G45_ID_PIOA) |
+ (1 << AT91SAM9G45_ID_PIOB) |
+ (1 << AT91SAM9G45_ID_PIOC) |
+ (1 << AT91SAM9G45_ID_PIODE), &pmc->pcer);
+
+ /* arch number of AT91SAM9M10G45EK-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_PM9G45;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ at91_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+ pm9g45_nand_hw_init();
+#endif
+
+#ifdef CONFIG_HAS_DATAFLASH
+ at91_spi0_hw_init(1 << 0);
+#endif
+
+#ifdef CONFIG_MACB
+ pm9g45_macb_hw_init();
+#endif
+
+#ifdef CONFIG_LCD
+ pm9g45_lcd_hw_init();
+#endif
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_MACB
+ /*
+ * Initialize ethernet HW addr prior to starting Linux,
+ * needed for nfsroot
+ */
+ eth_init(gd->bd);
+#endif
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_MACB
+ rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x01);
+#endif
+ return rc;
+}
diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h
new file mode 100644
index 0000000..fcd1754
--- /dev/null
+++ b/include/configs/pm9g45.h
@@ -0,0 +1,218 @@
+/*
+ * (C) Copyright 2010
+ * Ilko Iliev <il...@ronetix.at>
+ * Asen Dimov <di...@ronetix.at>
+ * Ronetix GmbH <www.ronetix.at>
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian....@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Configuation settings for the PM9G45 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* ARM asynchronous clock */
+#define AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal
*/
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
+#define CONFIG_PM9G45 1 /* It's an Ronetix PM9G45 */
+#define CONFIG_AT91SAM9G45 1 /* It's an Atmel AT91SAM9G45 SoC*/
+#define CONFIG_ARCH_CPU_INIT
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_AT91_GPIO 1
+#define CONFIG_ATMEL_USART 1
+#define CONFIG_USART3 1 /* USART 3 is DBGU */
+
+#define CONFIG_SYS_USE_NANDFLASH 1
+
+/*
+ * Hardware on board which could be removed
+ */
+#undef CONFIG_HAS_DATAFLASH
+
+/* LED */
+#define CONFIG_AT91_LED
+#define CONFIG_RED_LED AT91_PIO_PORTD, 31 /* this is the user1
led */
+#define CONFIG_GREEN_LED AT91_PIO_PORTD, 0 /* this is the user2
led */
+
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE 1
+#define CONFIG_BOOTP_BOOTPATH 1
+#define CONFIG_BOOTP_GATEWAY 1
+#define CONFIG_BOOTP_HOSTNAME 1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_CMD_PING 1
+#define CONFIG_CMD_DHCP 1
+#define CONFIG_CMD_NAND 1
+#define CONFIG_CMD_USB 1
+
+#define CONFIG_CMD_JFFS2 1
+#define CONFIG_JFFS2_CMDLINE 1
+#define CONFIG_JFFS2_NAND 1
+#define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */
+#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM 0x70000000
+#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
+
+/* DataFlash */
+#ifdef CONFIG_HAS_DATAFLASH
+#define CONFIG_ATMEL_DATAFLASH_SPI
+#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ)
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
+#define AT91_SPI_CLK 15000000
+#define DATAFLASH_TCSS (0x1a << 16)
+#define DATAFLASH_TCHS (0x1 << 24)
+#endif
+
+/* NOR flash, not available */
+#define CONFIG_SYS_NO_FLASH 1
+#undef CONFIG_CMD_FLASH
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_MAX_CHIPS 1
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CONFIG_SYS_NAND_DBW_8 1
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14
+#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTD, 3
+
+#endif
+
+/* Ethernet */
+#define CONFIG_MACB 1
+#define CONFIG_RMII 1
+#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_RETRY_COUNT 20
+#define CONFIG_RESET_PHY_R 1
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW 1
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /*
AT91SAM9G45_UHP_OHCI_BASE*/
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_STORAGE 1
+
+/* board specific(not enough SRAM) */
+#define CONFIG_AT91SAM9G45_LCD_BASE PHYS_SDRAM + 0xE00000
+
+#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM + 0x2000000 /* load address
*/
+
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END CONFIG_AT91SAM9G45_LCD_BASE
+
+#ifdef CONFIG_SYS_USE_DATAFLASH
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CONFIG_ENV_IS_IN_SPI_FLASH 1
+#define CONFIG_SYS_MONITOR_BASE (0xC0000000 + 0x8400)
+#define CONFIG_ENV_OFFSET 0x4200
+#define CONFIG_ENV_ADDR (0xC0000000 + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE 0x4200
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x72000000 0x210000; bootm"
+#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
+ "root=/dev/mtdblock0 " \
+ "mtdparts=atmel_nand:-(root) "\
+ "rw rootfstype=jffs2"
+
+#else /* CONFIG_SYS_USE_NANDFLASH */
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_IS_IN_NAND 1
+#define CONFIG_ENV_OFFSET 0x60000
+#define CONFIG_ENV_OFFSET_REDUND 0x80000
+#define CONFIG_ENV_SIZE 0x20000 /* 1 sector =
128 kB */
+#define CONFIG_BOOTCOMMAND "nand read 0x72000000 0x200000 0x200000; bootm"
+#define CONFIG_BOOTARGS "fbcon=rotate:3 console=tty0 " \
+ "console=ttyS0,115200 " \
+ "root=/dev/mtdblock4 " \
+ "mtdparts=atmel_nand:128k(bootstrap)ro," \
+ "256k(uboot)ro,1664k(env)," \
+ "2M(linux)ro,-(root) rw " \
+ "rootfstype=jffs2"
+
+#endif
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
+
+#define CONFIG_SYS_PROMPT "U-Boot> "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE +
sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024,
0x1000)
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
+
+#define CONFIG_STACKSIZE (32*1024) /* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
--
1.5.5.6
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