The Gen2 TMU is fed with fixed 32.5 MHz signal from CP . This is then divided by 4 in TMU. Fix the timer clock setting in Gen2.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com> --- include/configs/rcar-gen2-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index d606da8b0e..01583f8cc2 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -60,6 +60,6 @@ #define CONFIG_TMU_TIMER #define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ -#define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 8) +#define CONFIG_SYS_TIMER_RATE (32500000 / 4) /* CP/4 */ #endif /* __RCAR_GEN2_COMMON_H */ -- 2.18.0 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
