Hi Michael,
On Mon, Sep 3, 2018 at 10:05 AM, Michael Nazzareno Trimarchi
<mich...@amarulasolutions.com> wrote:
>> >> +static void ccgr_init(void)
>> >> +{
>> >> + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
>> >> +
>> >> + writel(0xFFFFFFFF, &ccm->CCGR0);
>> >> + writel(0xFFFFFFFF, &ccm->CCGR1);
>> >> + writel(0xFFFFFFFF, &ccm->CCGR2);
>> >> + writel(0xFFFFFFFF, &ccm->CCGR3);
>> >> + writel(0xFFFFFFFF, &ccm->CCGR4);
>> >> + writel(0xFFFFFFFF, &ccm->CCGR5);
>> >> + writel(0xFFFFFFFF, &ccm->CCGR6);
>> >> + writel(0xFFFFFFFF, &ccm->CCGR7);
>
> are you sure that arrive to 7?
You are right. CCGR7 is not available on mx6ul. I will fix it.
> I think that it's not a good strategy to enable all the gate in general here.
Yes, the main point of this patch is to convert from DCD table to SPL.
As the DCD table enables all the clocks I kept the same approach.
I agree that this can be further improved by only turning on the
clocks that are used by the bootloader.
However this is subject for a separate patch.
Thanks
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