On Mon, Aug 27, 2018 at 03:57:10PM +0530, Lokesh Vutla wrote: > On K3 family SoCs, once the ROM loads image on R5, M3 resets R5 and > expects to start executing from 0x0. In order to handle this ROM > updates the boot vector of R5 such that first 64 bytes of image load > address are mapped to 0x0. > > In this case, it is SPL's responsibility to jump to the proper image > location. So, update the PC with address of reset vector(like how > other exception vectors are handled), instead of branching to reset. > > Reviewed-by: Tom Rini <tr...@konsulko.com> > Signed-off-by: Lokesh Vutla <lokeshvu...@ti.com>
Applied to u-boot/master, thanks! -- Tom
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