Taken from coreboot's src/soc/rockchip/rk3288/sdram.c
Without this change, my u-boot build for the asus c201 chromebook (4GiB)
is incorrectly detected as 0 Bytes of ram.
Signed-off-by: Marty E. Plummer <hanet...@startmail.com>
---
arch/arm/mach-rockchip/sdram_common.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-rockchip/sdram_common.c
b/arch/arm/mach-rockchip/sdram_common.c
index 650d53e4d9..194dc74b9f 100644
--- a/arch/arm/mach-rockchip/sdram_common.c
+++ b/arch/arm/mach-rockchip/sdram_common.c
@@ -48,6 +48,8 @@ size_t rockchip_sdram_size(phys_addr_t reg)
rank, col, bk, cs0_row, bw, row_3_4);
}
+ size_mb = min(size_mb, SDRAM_MAX_SIZE/SZ_1M);
+
return (size_t)size_mb << 20;
}
--
2.18.0
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