On Sat, Oct 20, 2018 at 6:10 AM Lukas Auer <lukas.a...@aisec.fraunhofer.de> wrote: > > Implement the functions invalidate_icache_range() and > invalidate_icache_all(). > > RISC-V does not have instructions for explicit cache-control. The > functions in this patch are implemented with the memory ordering > instruction for synchronizing the instruction and data streams. This may > be implemented as a cache flush or invalidate on simple processors, > others may only invalidate the relevant cache lines. > > Signed-off-by: Lukas Auer <lukas.a...@aisec.fraunhofer.de> > --- > > arch/riscv/lib/cache.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) >
Reviewed-by: Bin Meng <bmeng...@gmail.com> _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
