Hi all. Starting with Monday I have access to an APL system (where I need to get coreboot running on). Maybe I can provide some additional information.
Am Sa., 24. Nov. 2018, 16:39 hat Bin Meng <bmeng...@gmail.com> geschrieben: > Hi Bernhard, > > On Fri, Nov 23, 2018 at 5:13 PM Bernhard Messerklinger > <bernhard.messerklin...@br-automation.com> wrote: > > > > Hi Bin, > > > > > Missing commit message > > I will fix this. > > > > > > APL means ApolloLake? Could you please spell it out? > > I will fix this. > > > > > > > Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br- > > > automation.com> > > > > --- > > > > > > > > drivers/timer/tsc_timer.c | 2 ++ > > > > 1 file changed, 2 insertions(+) > > > > > > > > diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c > > > > index da7c812908..b2a982812a 100644 > > > > --- a/drivers/timer/tsc_timer.c > > > > +++ b/drivers/timer/tsc_timer.c > > > > @@ -64,6 +64,8 @@ static struct freq_desc freq_desc_tables[] = { > > > > 80000, 93300, 90000, 88900, 87500 } }, > > > > /* Ivybridge */ > > > > { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, > > > > + /* Intel Atom processor E3900 series */ > > > > + { 6, 0x5c, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, > > > > > > Please avoid hardcoding TSC freq this way. Isn't calibrating from MSR > > > not working for ApolloLake? > > I found two ways to get the TSC freq. > > 1. Read the necessary parameters with cpuid(instruction 15) like it is > > done in > > the kernel. > > The problem with this way is that for some reason my core crystal clock > is > > > > > > always set to zero, so I would need to add the crystal frequency > > somewhere. > > The TSC timer supports 3 ways of calibrating frequency: > cpu_mhz_from_cpuid(), cpu_mhz_from_msr() and quick_pit_calibrate(). > > Are you saying that if doing cpu_mhz_from_cpuid() you can't get > correct frequency? Can you investigate why your core crystal clock is > always zero? > > > 2. Read it from MSR. > > That?s actually the way I do it in this patch. I only need to add my cpu > > family/model to avoid return with 0 at the begin of cpu_mhz_from_msr. > > > > Please tell me if I overlook something. > > > > For the MSR, I meant to say the table below: > > static struct freq_desc freq_desc_tables[] = { > /* PNW */ > { 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200, 0 } }, > /* CLV+ */ > { 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200, 0 } }, > /* TNG - Intel Atom processor Z3400 series */ > { 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0, 0 } }, > /* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */ > { 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0, 0 } }, > /* ANN - Intel Atom processor Z3500 series */ > { 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0, 0 } }, > /* AMT - Intel Atom processor X7-Z8000 and X5-Z8000 series */ > { 6, 0x4c, 1, { 83300, 100000, 133300, 116700, > 80000, 93300, 90000, 88900, 87500 } }, > /* Ivybridge */ > { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, > }; > > Can we do it something like VLV2? > > Regards, > Bin > Greets -- Christian Gmeiner, MSc https://christian-gmeiner.info _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot