>> Does it mean I have to CFI_MTD ot common CFI_DRIVER will works? > > I don't understand this question. >
me neither >> *----------------------------------------------------------------------*/ >> #define CONFIG_SYS_FLASH_CFI >> #define CONFIG_FLASH_CFI_DRIVER >> #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on >> flinfo */ >> >> #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} >> #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ >> #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ >> #define CONFIG_FLASH_SHOW_PROGRESS 1 >> >> #define CONFIG_SYS_FLASH_ERASE_TOUT 220000 /* Timeout for Flash Erase (in >> ms) */ >> #define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Timeout for Flash Write (in >> ms) */ >> >> #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ >> #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) >> #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ > > This looks good. With these defines the CFI driver should work. You might want > to add CONFIG_SYS_FLASH_USE_BUFFER_WRITE for write speedup. And you need to > configure your access timing for the chip select to the NOR Chip correctly of > course. > Yes, we use #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1, on order to speed write ops. Our BR- and OR setting is very conservative since some signals are routed through an FPGA and are delayed. For this reason, we utilize 8 wait states. Frank _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot