On 11/27/2018 04:45 AM, Masahiro Yamada wrote: > On Tue, Nov 27, 2018 at 6:35 AM Marek Vasut <marek.va...@gmail.com> wrote: >> >> On 11/14/2018 12:40 AM, Marek Vasut wrote: >>> Switch the driver to using clk_get_rate()/clk_set_rate() instead of >>> caching the mclk frequency in it's private data. This is required on >>> the SDHI variant of the controller, where the upstream mclk need to >>> be adjusted when using UHS modes. >>> >>> Platforms which do not support clock framework or do not support it >>> in eg. SPL default to 100 MHz clock. >>> >>> Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com> >>> Cc: Masahiro Yamada <yamada.masah...@socionext.com> >> >> Yamada-san, can you please check 1/6..3/6 ? > > > Not tested, but 1/6, 2/6 look good. > I left comments in 3/6.
You can grab the whole bulk at [1] and test it if you want. There are some extra renesas-specific bits, but those shouldn't affect you. btw is there any chance to buy a uniphier board with TMIO SD controller? [1] https://github.com/marex/u-boot-sh/commits/mmc-next-v4 -- Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot