On 11/23/2018 05:47 PM, Martyn Welch wrote: > Port for the PHYTEC phyBOARD-i.MX6UL-Segin single board computer. Based on > the PHYTEC phyCORE-i.MX6UL SOM (PCL063).
Nice ! A few nits below. > This port provides both SPL and > DCD based boot options (hence the two defconfigs). Is the DCD option really needed or can it be dropped ? The SPL is far more flexible. > CPU: Freescale i.MX6UL rev1.2 528 MHz (running at 396 MHz) > CPU: Industrial temperature grade (-40C to 105C) at 44C > Reset cause: POR > Board: PHYTEC phyCORE-i.MX6UL > I2C: ready > DRAM: 256 MiB > NAND: 512 MiB > MMC: FSL_SDHC: 0 > In: serial > Out: serial > Err: serial > Net: FEC0 > > Working: > - Eth0 > - i2C > - MMC/SD > - NAND > - UART (1 & 5) > - USB (host & otg) > > Signed-off-by: Martyn Welch <martyn.we...@collabora.com> > > --- > > Changes in v2: > - Switch to driver model > > arch/arm/dts/Makefile | 3 +- > arch/arm/dts/imx6ul-pcl063.dtsi | 180 ++++++++++++++++++++++ > arch/arm/dts/imx6ul-phycore-segin.dts | 76 ++++++++++ > arch/arm/mach-imx/mx6/Kconfig | 13 ++ > board/phytec/pcl063/Kconfig | 12 ++ > board/phytec/pcl063/MAINTAINERS | 9 ++ > board/phytec/pcl063/Makefile | 7 + > board/phytec/pcl063/README | 43 ++++++ > board/phytec/pcl063/imximage.cfg | 177 ++++++++++++++++++++++ > board/phytec/pcl063/pcl063.c | 206 ++++++++++++++++++++++++++ > board/phytec/pcl063/spl.c | 118 +++++++++++++++ > configs/phycore_pcl063_defconfig | 66 +++++++++ > configs/phycore_pcl063_spl_defconfig | 71 +++++++++ > include/configs/pcl063.h | 100 +++++++++++++ > 14 files changed, 1080 insertions(+), 1 deletion(-) > create mode 100644 arch/arm/dts/imx6ul-pcl063.dtsi > create mode 100644 arch/arm/dts/imx6ul-phycore-segin.dts > create mode 100644 board/phytec/pcl063/Kconfig > create mode 100644 board/phytec/pcl063/MAINTAINERS > create mode 100644 board/phytec/pcl063/Makefile > create mode 100644 board/phytec/pcl063/README > create mode 100644 board/phytec/pcl063/imximage.cfg > create mode 100644 board/phytec/pcl063/pcl063.c > create mode 100644 board/phytec/pcl063/spl.c > create mode 100644 configs/phycore_pcl063_defconfig > create mode 100644 configs/phycore_pcl063_spl_defconfig > create mode 100644 include/configs/pcl063.h > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > index d36447d18d..ffda97a291 100644 > --- a/arch/arm/dts/Makefile > +++ b/arch/arm/dts/Makefile > @@ -444,7 +444,8 @@ dtb-$(CONFIG_MX6UL) += \ > imx6ul-isiot-nand.dtb \ > imx6ul-opos6uldev.dtb \ > imx6ul-14x14-evk.dtb \ > - imx6ul-9x9-evk.dtb > + imx6ul-9x9-evk.dtb \ > + imx6ul-phycore-segin.dtb > > dtb-$(CONFIG_MX6ULL) += imx6ull-14x14-evk.dtb > > diff --git a/arch/arm/dts/imx6ul-pcl063.dtsi b/arch/arm/dts/imx6ul-pcl063.dtsi > new file mode 100644 > index 0000000000..fa63911480 > --- /dev/null > +++ b/arch/arm/dts/imx6ul-pcl063.dtsi > @@ -0,0 +1,180 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2018 Collabora Ltd. > + * > + * Based on dts[i] from Phytech barebox port: "Phytec", fix globally. But maybe you can pull the DT from upstream Linux instead ? > + * Copyright (C) 2016 PHYTEC Messtechnik GmbH > + * Author: Christian Hemp <c.h...@phytec.de> > + * > + * The code contained herein is licensed under the GNU General Public > + * License. You may obtain a copy of the GNU General Public License > + * Version 2 or later at the following locations: This is in the SPDX tag above, drop it. [...] > +int board_init(void) > +{ > + /* Address of boot parameters */ > + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; > + > +#ifdef CONFIG_NAND_MXS > + setup_gpmi_nand(); > +#endif > + > +#ifdef CONFIG_FEC_MXC ifdef[SPACE] instead of TAB, keep it consistent. > + setup_fec(); > +#endif > + return 0; > +} [...] -- Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot