On Mon, Dec 31, 2018 at 2:28 AM Lukas Auer <lukas.a...@aisec.fraunhofer.de> wrote: > > The fence instruction is used to enforce device I/O and memory ordering > constraints in RISC-V. It does not directly affect the data cache and > particular cannot be used to flush or invalidate it. RISC-V does not > have instructions for explicit cache control. Remove the > flush_dcache_all implementation and its use in all dcache-specific > functions in lib/cache.c. > > This also adds a missing new line between flush_dcache_all and > flush_dcache_range in lib/cache.c. > > Signed-off-by: Lukas Auer <lukas.a...@aisec.fraunhofer.de> > --- > This patch only removes the implementation itself and its use in > dcache-specific functions in lib/cache.c. There are more uses of it in > arch/riscv/, which this patch does not remove. > > arch/riscv/lib/cache.c | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions(-) >
Reviewed-by: Bin Meng <bmeng...@gmail.com> _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
