On Fri, Jan 4, 2019 at 8:38 AM Lukas Auer <lukas.a...@aisec.fraunhofer.de> wrote: > > The fence instruction is used to enforce device I/O and memory ordering > constraints in RISC-V. It can not be relied on to directly affect the > data cache on every CPU. > Andes' AX25 does not have a coherence agent. Its fence instruction > flushes the data cache and is used to keep data in the system coherent. > The implementation of flush_dcache_all in lib/cache.c is therefore > specific to the AX25. Move it into the AX25-specific cache.c in > cpu/ax25/. > > This also adds a missing new line between flush_dcache_all and > flush_dcache_range in lib/cache.c. > > Signed-off-by: Lukas Auer <lukas.a...@aisec.fraunhofer.de> > --- > > Changes in v2: > - Replace patch "riscv: remove invalid dcache flush implementation" with > new patch "riscv: move the AX25-specific implementation of > flush_dcache_all" >
Reviewed-by: Bin Meng <bmeng...@gmail.com> _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot