Create sysreset driver for Jaguar2 SOC family and update defconfig
to use it.
Signed-off-by: Horatiu Vultur <horatiu.vul...@microchip.com>
---
MAINTAINERS | 1 +
board/mscc/jr2/jr2.c | 8 +++++++
configs/mscc_jr2_defconfig | 2 ++
drivers/sysreset/Kconfig | 6 ++++++
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_jr2.c | 46 +++++++++++++++++++++++++++++++++++++++++
6 files changed, 64 insertions(+)
create mode 100644 drivers/sysreset/sysreset_jr2.c
diff --git a/MAINTAINERS b/MAINTAINERS
index d42736b..8b8cc9d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -526,6 +526,7 @@ F: arch/mips/dts/serval*
F: board/mscc/
F: configs/mscc*
F: drivers/gpio/mscc_sgpio.c
+F: drivers/sysreset/sysreset_jr2.c
F: include/configs/vcoreiii.h
F: drivers/pinctrl/mscc/
diff --git a/board/mscc/jr2/jr2.c b/board/mscc/jr2/jr2.c
index 36f9896..2935ad0 100644
--- a/board/mscc/jr2/jr2.c
+++ b/board/mscc/jr2/jr2.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <asm/io.h>
#include <led.h>
+#include <dm/lists.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -17,6 +18,8 @@ enum {
int board_early_init_r(void)
{
+ int ret;
+
/* Prepare SPI controller to be used in master mode */
writel(0, BASE_CFG + ICPU_SW_MODE);
clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
@@ -30,6 +33,11 @@ int board_early_init_r(void)
if (IS_ENABLED(CONFIG_LED))
led_default_state();
+ ret = device_bind_driver(gd->dm_root, "jr2_soft_reset",
+ "reset_soft", NULL);
+ if (ret)
+ printf("Warning: No reset driver: ret=%d\n", ret);
+
return 0;
}
diff --git a/configs/mscc_jr2_defconfig b/configs/mscc_jr2_defconfig
index b215754..e80dde6 100644
--- a/configs/mscc_jr2_defconfig
+++ b/configs/mscc_jr2_defconfig
@@ -57,3 +57,5 @@ CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_LZMA=y
CONFIG_XZ=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_JR2=y
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 8ce3e2e..7c6db0f 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -43,6 +43,12 @@ config SYSRESET_TI_SCI
This enables the system reset driver support over TI System Control
Interface available on some new TI's SoCs.
+config SYSRESET_JR2
+ bool "Enable support for Jaguar2 soft reset"
+ depends on SOC_JR2
+ help
+ This is soft reset on Jaguar2.
+
endif
config SYSRESET_SYSCON
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index b3728ac..24c488b 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -16,3 +16,4 @@ obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o
obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
obj-$(CONFIG_SYSRESET_X86) += sysreset_x86.o
obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o
+obj-$(CONFIG_SYSRESET_JR2) += sysreset_jr2.o
diff --git a/drivers/sysreset/sysreset_jr2.c b/drivers/sysreset/sysreset_jr2.c
new file mode 100644
index 0000000..76a5bac
--- /dev/null
+++ b/drivers/sysreset/sysreset_jr2.c
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi SoCs pinctrl driver
+ *
+ * Author: <horatiu.vul...@microchip.com>
+ * License: Dual MIT/GPL
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <linux/err.h>
+#include <asm/io.h>
+
+static int jr2_sysreset_request(struct udevice *dev,
+ enum sysreset_t type)
+{
+ register u32 reg = readl(BASE_CFG + ICPU_GENERAL_CTRL);
+ /* Set owner */
+ reg &= ~ICPU_GENERAL_CTRL_IF_SI_OWNER_M;
+ reg |= ICPU_GENERAL_CTRL_IF_SI_OWNER(1);
+ /* Set boot mode */
+ reg |= ICPU_GENERAL_CTRL_BOOT_MODE_ENA;
+ writel(reg, BASE_CFG + ICPU_GENERAL_CTRL);
+ /* Read back in order to make BOOT mode setting active */
+ reg = readl(BASE_CFG + ICPU_GENERAL_CTRL);
+ /* Reset CPU only - still executing _here_. but from cache */
+ writel(readl(BASE_CFG + ICPU_RESET) |
+ ICPU_RESET_CORE_RST_CPU_ONLY |
+ ICPU_RESET_CORE_RST_FORCE,
+ BASE_CFG + ICPU_RESET);
+
+ return -EINPROGRESS;
+}
+
+static struct sysreset_ops jr2_sysreset = {
+ .request = jr2_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_jr2) = {
+ .id = UCLASS_SYSRESET,
+ .name = "jr2_soft_reset",
+ .ops = &jr2_sysreset,
+};
--
2.7.4
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