[U-Boot] [PATCH v1 1/5] arm: mach-snapdragon: db820c: Actually init PLL for serial

[Ramon Fried]

The PLL for the UART was not set, and relied on previous
initializtion made by LK. add the appropriate initialization.

Signed-off-by: Ramon Fried <ramon.fr...@gmail.com>
---

 arch/arm/mach-snapdragon/clock-apq8096.c      | 34 +++++++++++++++++++
 .../include/mach/sysmap-apq8096.h             |  9 +++++
 2 files changed, 43 insertions(+)

diff --git a/arch/arm/mach-snapdragon/clock-apq8096.c 
b/arch/arm/mach-snapdragon/clock-apq8096.c
index 628c38785b..e5011be8f2 100644
--- a/arch/arm/mach-snapdragon/clock-apq8096.c
+++ b/arch/arm/mach-snapdragon/clock-apq8096.c
@@ -34,6 +34,12 @@ static const struct pll_vote_clk gpll0_vote_clk = {
        .vote_bit = APCS_GPLL_ENA_VOTE_GPLL0,
 };
 
+static struct vote_clk gcc_blsp2_ahb_clk = {
+       .cbcr_reg = BLSP2_AHB_CBCR,
+       .ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE,
+       .vote_bit = BIT(15),
+};
+
 static int clk_init_sdc(struct msm_clk_priv *priv, uint rate)
 {
        int div = 3;
@@ -47,6 +53,32 @@ static int clk_init_sdc(struct msm_clk_priv *priv, uint rate)
        return rate;
 }
 
+static const struct bcr_regs uart2_regs = {
+       .cfg_rcgr = BLSP2_UART2_APPS_CFG_RCGR,
+       .cmd_rcgr = BLSP2_UART2_APPS_CMD_RCGR,
+       .M = BLSP2_UART2_APPS_M,
+       .N = BLSP2_UART2_APPS_N,
+       .D = BLSP2_UART2_APPS_D,
+};
+
+static int clk_init_uart(struct msm_clk_priv *priv)
+{
+       /* Enable AHB clock */
+       clk_enable_vote_clk(priv->base, &gcc_blsp2_ahb_clk);
+
+       /* 7372800 uart block clock @ GPLL0 */
+       clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 192, 15625,
+                            CFG_CLK_SRC_GPLL0);
+
+       /* Vote for gpll0 clock */
+       clk_enable_gpll0(priv->base, &gpll0_vote_clk);
+
+       /* Enable core clk */
+       clk_enable_cbc(priv->base + BLSP2_UART2_APPS_CBCR);
+
+       return 0;
+}
+
 ulong msm_set_rate(struct clk *clk, ulong rate)
 {
        struct msm_clk_priv *priv = dev_get_priv(clk->dev);
@@ -55,6 +87,8 @@ ulong msm_set_rate(struct clk *clk, ulong rate)
        case 0: /* SDC1 */
                return clk_init_sdc(priv, rate);
                break;
+       case 4: /*UART2*/
+               return clk_init_uart(priv);
        default:
                return 0;
        }
diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h 
b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h
index 14febb6487..36a902bd92 100644
--- a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h
+++ b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h
@@ -15,6 +15,7 @@
 /* Clocks: (from CLK_CTL_BASE)  */
 #define GPLL0_STATUS                   (0x0000)
 #define APCS_GPLL_ENA_VOTE             (0x52000)
+#define APCS_CLOCK_BRANCH_ENA_VOTE     (0x52004)
 
 #define SDCC2_BCR                      (0x14000) /* block reset */
 #define SDCC2_APPS_CBCR                        (0x14004) /* branch control */
@@ -25,4 +26,12 @@
 #define SDCC2_N                                (0x1401C)
 #define SDCC2_D                                (0x14020)
 
+#define BLSP2_AHB_CBCR                 (0x25004)
+#define BLSP2_UART2_APPS_CBCR          (0x29004)
+#define BLSP2_UART2_APPS_CMD_RCGR      (0x2900C)
+#define BLSP2_UART2_APPS_CFG_RCGR      (0x29010)
+#define BLSP2_UART2_APPS_M             (0x29014)
+#define BLSP2_UART2_APPS_N             (0x29018)
+#define BLSP2_UART2_APPS_D             (0x2901C)
+
 #endif
-- 
2.20.1

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