Unlike other Allwinner SoC's, H6 comes with different
clock and reset control offset values. So support them
via driver data.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
.../arm/include/asm/arch-sunxi/clock_sun50i_h6.h | 3 +++
drivers/mmc/sunxi_mmc.c | 16 ++++++++++++++++
2 files changed, 19 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
index e36937059b..baf9b2e6e2 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
@@ -301,6 +301,9 @@ struct sunxi_ccm_reg {
#define DRAM_CLK_SRC_PLL5 (0 << 24)
#define DRAM_CLK_M(m) (((m)-1) << 0)
+/* MMC ahb clock bit field */
+#define AHB_GATE_OFFSET_MMC(n) ((n))
+
/* MMC clock bit field */
#define CCM_MMC_CTRL_M(x) ((x) - 1)
#define CCM_MMC_CTRL_N(x) ((x) << 8)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index b1c177bba3..5b9ac5f82c 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -697,6 +697,14 @@ static const struct sunxi_mmc_variant sun7i_a20_variant = {
.reset_start_bit = 8,
};
+static const struct sunxi_mmc_variant sun50i_h6_variant = {
+ .has_reset = true,
+ .gate_offset = 0x84c,
+ .mclk_offset = 0x830,
+ .reset_offset = 0x84c,
+ .reset_start_bit = 16,
+};
+
static const struct udevice_id sunxi_mmc_ids[] = {
{
.compatible = "allwinner,sun4i-a10-mmc",
@@ -722,6 +730,14 @@ static const struct udevice_id sunxi_mmc_ids[] = {
.compatible = "allwinner,sun50i-a64-emmc",
.data = (ulong)&sun7i_a20_variant,
},
+ {
+ .compatible = "allwinner,sun50i-h6-mmc",
+ .data = (ulong)&sun50i_h6_variant,
+ },
+ {
+ .compatible = "allwinner,sun50i-h6-emmc",
+ .data = (ulong)&sun50i_h6_variant,
+ },
{ /* sentinel */ }
};
--
2.18.0.321.gffc6fa0e3
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