The SPL for socfpga gen5 currently takes all peripherals out of reset
unconditionally. To implement proper reset handling for peripherals,
some device tree nodes are missing reset handles.
Since the socfpga gen5 devicetrees are currently in sync with Linux 4.20,
and these reset handles are not added to Linux, yet, let's add them to
U-Boot specific dtsi files to ease future merging.
This adds a new file socfpga_u-boot.dtsi (note the '_' - if using a '-'
this file gets pulled in for some a10/s10 devicetrees) that adds the
missing reset handles.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschm...@gmail.com>
---
arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi | 6 ++
arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts | 5 ++
.../socfpga_cyclone5_de0_nano_soc-u-boot.dtsi | 6 ++
arch/arm/dts/socfpga_cyclone5_de10_nano.dts | 5 ++
arch/arm/dts/socfpga_cyclone5_de1_soc.dts | 5 ++
arch/arm/dts/socfpga_cyclone5_is1.dts | 5 ++
.../dts/socfpga_cyclone5_socdk-u-boot.dtsi | 6 ++
.../dts/socfpga_cyclone5_sockit-u-boot.dtsi | 6 ++
.../dts/socfpga_cyclone5_socrates-u-boot.dtsi | 10 +++
arch/arm/dts/socfpga_cyclone5_sr1500.dts | 5 ++
.../socfpga_cyclone5_vining_fpga-u-boot.dtsi | 6 ++
arch/arm/dts/socfpga_u-boot.dtsi | 61 +++++++++++++++++++
12 files changed, 126 insertions(+)
create mode 100644 arch/arm/dts/socfpga_u-boot.dtsi
diff --git a/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
index c44d1ee2fa..b4cd73d367 100644
--- a/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
@@ -6,6 +6,8 @@
* Copyright (c) 2018 Simon Goldschmidt
*/
+#include "socfpga_u-boot.dtsi"
+
/{
aliases {
spi0 = "/soc/spi@ff705000";
@@ -17,6 +19,10 @@
};
};
+&rst {
+ u-boot,dm-pre-reloc;
+};
+
&watchdog0 {
status = "disabled";
};
diff --git a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
index a387071674..f616740981 100644
--- a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
+++ b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
@@ -4,6 +4,7 @@
*/
#include "socfpga_cyclone5.dtsi"
+#include "socfpga_u-boot.dtsi"
/ {
model = "Devboards.de DBM-SoC1";
@@ -30,6 +31,10 @@
};
};
+&rst {
+ u-boot,dm-pre-reloc;
+};
+
&gmac1 {
status = "okay";
phy-mode = "rgmii";
diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi
b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi
index 08d81da169..63dd0de23b 100644
--- a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi
@@ -6,6 +6,8 @@
* Copyright (c) 2018 Simon Goldschmidt
*/
+#include "socfpga_u-boot.dtsi"
+
/{
aliases {
udc0 = &usb1;
@@ -16,6 +18,10 @@
};
};
+&rst {
+ u-boot,dm-pre-reloc;
+};
+
&watchdog0 {
status = "disabled";
};
diff --git a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
index e9105743ea..7106b0300a 100644
--- a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
+++ b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
@@ -6,6 +6,7 @@
*/
#include "socfpga_cyclone5.dtsi"
+#include "socfpga_u-boot.dtsi"
/ {
model = "Terasic DE10-Nano";
@@ -32,6 +33,10 @@
};
};
+&rst {
+ u-boot,dm-pre-reloc;
+};
+
&gmac1 {
status = "okay";
phy-mode = "rgmii";
diff --git a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
index 4f076bce93..5d426dad68 100644
--- a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
+++ b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
@@ -4,6 +4,7 @@
*/
#include "socfpga_cyclone5.dtsi"
+#include "socfpga_u-boot.dtsi"
/ {
model = "Terasic DE1-SoC";
@@ -30,6 +31,10 @@
};
};
+&rst {
+ u-boot,dm-pre-reloc;
+};
+
&gmac1 {
status = "okay";
phy-mode = "rgmii";
diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts
b/arch/arm/dts/socfpga_cyclone5_is1.dts
index b7054bfd5a..3383754cb4 100644
--- a/arch/arm/dts/socfpga_cyclone5_is1.dts
+++ b/arch/arm/dts/socfpga_cyclone5_is1.dts
@@ -4,6 +4,7 @@
*/
#include "socfpga_cyclone5.dtsi"
+#include "socfpga_u-boot.dtsi"
/ {
model = "SoCFPGA Cyclone V IS1";
@@ -37,6 +38,10 @@
};
};
+&rst {
+ u-boot,dm-pre-reloc;
+};
+
&gmac1 {
status = "okay";
phy-mode = "rgmii";
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
index 9436e0fa8b..0c39017d55 100644
--- a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
@@ -6,6 +6,8 @@
* Copyright (c) 2018 Simon Goldschmidt
*/
+#include "socfpga_u-boot.dtsi"
+
/{
aliases {
spi0 = "/soc/spi@ff705000";
@@ -17,6 +19,10 @@
};
};
+&rst {
+ u-boot,dm-pre-reloc;
+};
+
&can0 {
status = "okay";
};
diff --git a/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi
b/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi
index 648f1bd01d..284e19a66f 100644
--- a/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi
@@ -6,6 +6,8 @@
* Copyright (c) 2018 Simon Goldschmidt
*/
+#include "socfpga_u-boot.dtsi"
+
/{
aliases {
spi0 = "/soc/spi@ff705000";
@@ -17,6 +19,10 @@
};
};
+&rst {
+ u-boot,dm-pre-reloc;
+};
+
&watchdog0 {
status = "disabled";
};
diff --git a/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi
b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi
index 31bd1dba0f..4a0ca813cb 100644
--- a/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi
@@ -6,6 +6,8 @@
* Copyright (c) 2018 Simon Goldschmidt
*/
+#include "socfpga_u-boot.dtsi"
+
/{
aliases {
spi0 = "/soc/spi@ff705000";
@@ -17,10 +19,18 @@
};
};
+&rst {
+ u-boot,dm-pre-reloc;
+};
+
&watchdog0 {
status = "disabled";
};
+&rst {
+ u-boot,dm-pre-reloc;
+};
+
&mmc {
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/socfpga_cyclone5_sr1500.dts
b/arch/arm/dts/socfpga_cyclone5_sr1500.dts
index 6a6c29be79..0025baf29e 100644
--- a/arch/arm/dts/socfpga_cyclone5_sr1500.dts
+++ b/arch/arm/dts/socfpga_cyclone5_sr1500.dts
@@ -4,6 +4,7 @@
*/
#include "socfpga_cyclone5.dtsi"
+#include "socfpga_u-boot.dtsi"
/ {
model = "SoCFPGA Cyclone V SR1500";
@@ -33,6 +34,10 @@
};
};
+&rst {
+ u-boot,dm-pre-reloc;
+};
+
&gmac1 {
status = "okay";
phy-mode = "rgmii";
diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
index 360b946ba2..4a24fcdacd 100644
--- a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
@@ -6,6 +6,8 @@
* Copyright (c) 2018 Simon Goldschmidt
*/
+#include "socfpga_u-boot.dtsi"
+
/{
aliases {
spi0 = "/soc/spi@ff705000";
@@ -17,6 +19,10 @@
};
};
+&rst {
+ u-boot,dm-pre-reloc;
+};
+
&watchdog0 {
status = "disabled";
};
diff --git a/arch/arm/dts/socfpga_u-boot.dtsi b/arch/arm/dts/socfpga_u-boot.dtsi
new file mode 100644
index 0000000000..1abd8ec41b
--- /dev/null
+++ b/arch/arm/dts/socfpga_u-boot.dtsi
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (c) 2019 Simon Goldschmidt
+ *
+ * Note: this file deliberately is not named "-u-boot.dtsi" to prevent it
+ * getting auto-included for non-gen5 socfpga devicetrees.
+ */
+
+&pdma {
+ resets = <&rst DMA_RESET>;
+};
+
+&can0 {
+ resets = <&rst CAN0_RESET>;
+};
+
+&can1 {
+ resets = <&rst CAN1_RESET>;
+};
+
+&gpio0 {
+ resets = <&rst GPIO0_RESET>;
+};
+
+&gpio1 {
+ resets = <&rst GPIO1_RESET>;
+};
+
+&gpio2 {
+ resets = <&rst GPIO2_RESET>;
+};
+
+&mmc {
+ resets = <&rst SDMMC_RESET>;
+};
+
+&nand0 {
+ resets = <&rst NAND_RESET>;
+};
+
+&qspi {
+ resets = <&rst QSPI_RESET>;
+};
+
+&spi0 {
+ resets = <&rst SPIM0_RESET>;
+};
+
+&spi1 {
+ resets = <&rst SPIM1_RESET>;
+};
+
+&uart0 {
+ resets = <&rst UART0_RESET>;
+};
+
+&uart1 {
+ resets = <&rst UART1_RESET>;
+};
--
2.17.1
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