From: Vaibhav Hiremath <hvaib...@ti.com>
The patch makes sure that size for SDRC CS1 gets calculated
only when the CS1 SDRC is initialized.
Signed-off-by: Vaibhav Hiremath <hvaib...@ti.com>
Signed-off-by: Sanjeev Premi <pr...@ti.com>
---
arch/arm/cpu/arm_cortexa8/omap3/board.c | 7 ++++---
1 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/board.c
b/arch/arm/cpu/arm_cortexa8/omap3/board.c
index 7b78fa4..69a08fd 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/board.c
+++ b/arch/arm/cpu/arm_cortexa8/omap3/board.c
@@ -282,6 +282,8 @@ int dram_init(void)
DECLARE_GLOBAL_DATA_PTR;
unsigned int size0 = 0, size1 = 0;
+ size0 = get_sdr_cs_size(CS0);
+
/*
* If a second bank of DDR is attached to CS1 this is
* where it can be started. Early init code will init
@@ -290,10 +292,9 @@ int dram_init(void)
if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
do_sdrc_init(CS1, NOT_EARLY);
make_cs1_contiguous();
- }
- size0 = get_sdr_cs_size(CS0);
- size1 = get_sdr_cs_size(CS1);
+ size1 = get_sdr_cs_size(CS1);
+ }
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = size0;
--
1.6.2.4
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