On 31/01/19 7:20 PM, Jagan Teki wrote: > On Thu, 31 Jan, 2019, 7:16 PM Vignesh R <vigne...@ti.com > <mailto:vigne...@ti.com> wrote: > > On 31/01/19 7:06 PM, Jagan Teki wrote: > [...] > > >> configs/xilinx_zynqmp_mini_qspi_defconfig | 1 - > > >> configs/xilinx_zynqmp_zc1232_revA_defconfig | 1 - > > >> configs/xilinx_zynqmp_zc1254_revA_defconfig | 1 - > > >> configs/xilinx_zynqmp_zc1275_revA_defconfig | 1 - > > >> configs/xilinx_zynqmp_zc1275_revB_defconfig | 1 - > > >> configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 - > > >> configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 - > > >> configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 1 - > > >> configs/xilinx_zynqmp_zcu100_revC_defconfig | 1 - > > >> configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 1 - > > >> configs/xilinx_zynqmp_zcu102_revA_defconfig | 1 - > > >> configs/xilinx_zynqmp_zcu102_revB_defconfig | 1 - > > >> configs/xilinx_zynqmp_zcu104_revA_defconfig | 1 - > > >> configs/xilinx_zynqmp_zcu104_revC_defconfig | 1 - > > >> configs/xilinx_zynqmp_zcu106_revA_defconfig | 1 - > > >> configs/xilinx_zynqmp_zcu111_revA_defconfig | 1 - > > >> configs/zynq_cc108_defconfig | 1 - > > >> configs/zynq_cse_qspi_defconfig | 1 - > > >> configs/zynq_dlc20_rev1_0_defconfig | 1 - > > >> configs/zynq_microzed_defconfig | 1 - > > >> configs/zynq_minized_defconfig | 1 - > > >> configs/zynq_z_turn_defconfig | 1 - > > >> configs/zynq_zc702_defconfig | 1 - > > >> configs/zynq_zc706_defconfig | 1 - > > >> configs/zynq_zc770_xm010_defconfig | 1 - > > >> configs/zynq_zc770_xm013_defconfig | 1 - > > >> configs/zynq_zed_defconfig | 1 - > > >> configs/zynq_zybo_defconfig | 1 - > > >> configs/zynq_zybo_z7_defconfig | 1 - > > > > > > zynq targets do need BAR, same has commented in previous mails. > > > > Hmmm, Is this a limitation of SPI controller on the SoC or > flash on the > > board? > > AFAICS, zynq_spi.c, zynq_qspi.c zynq_spi.c zynqmp_gqspi.c are > all FIFO > > based SPI controllers and ideally should not care about > address length. > > Could you please explain why BAR is a requirement on these > platforms? > > > > Were you able to test this series on any of those platforms? > > > > > > Go back to the log history, initial intension for adding BAR was > on zynq. > > > > > Sorry, this is all I could find from mailing list (original series by > you that adds BAR support): > https://lists.denx.de/pipermail/u-boot/2013-June/157006.html > > There is nothing that mentions why Zynq platforms need BAR support and > cannot use 4 byte opcodes to access >16MB space? > > > Yes, zynq qspi ia unable to handle larger than 16MiB flashes so we used > BAR to access those. >
I wonder how those boards work in kernel that does not support BAR. Anyways, if you provide a list of SPI controllers on zynq SoCs, I will add an imply SPI_FLASH_BAR for such Kconfigs and send a separate patch. > Michal, Siva: can you confirm? > > -- Regards Vignesh _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
