EPHY CLK and RESET is availble in Allwinner H3 EMAC via mdio-mux node of internal PHY. Add the respetive clock and reset reg and bits.
Cc: Joe Hershberger <joe.hershber...@ni.com> Signed-off-by: Jagan Teki <ja...@amarulasolutions.com> --- drivers/clk/sunxi/clk_h3.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c index f5ae1e9555..6111a13f1c 100644 --- a/drivers/clk/sunxi/clk_h3.c +++ b/drivers/clk/sunxi/clk_h3.c @@ -34,6 +34,8 @@ static struct ccu_clk_gate h3_gates[] = { [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), [CLK_BUS_UART3] = GATE(0x06c, BIT(19)), + [CLK_BUS_EPHY] = GATE(0x070, BIT(0)), + [CLK_SPI0] = GATE(0x0a0, BIT(31)), [CLK_SPI1] = GATE(0x0a4, BIT(31)), @@ -69,6 +71,8 @@ static struct ccu_reset h3_resets[] = { [RST_BUS_OHCI2] = RESET(0x2c0, BIT(30)), [RST_BUS_OHCI3] = RESET(0x2c0, BIT(31)), + [RST_BUS_EPHY] = RESET(0x2c8, BIT(2)), + [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), -- 2.18.0.321.gffc6fa0e3 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot