Hi Maxime On Wed, Feb 13, 2019 at 9:44 AM Maxime Ripard <maxime.rip...@bootlin.com> wrote: > > On Tue, Feb 12, 2019 at 05:57:07PM +0100, Michael Trimarchi wrote: > > Change the size create a glitch in the clke signal on second > > bank. > > Which glitch? > > > The glitch can generate problem in memory initialiazation > > Which problem? on which board? How do we reproduce it?
Yes I know. I'm working on production of a device and fix some failing board. You can check the glitch here. I will adjust the commit soon. A33, 2GB, double rank Michael > > Maxime > > -- > Maxime Ripard, Bootlin > Embedded Linux and Kernel engineering > https://bootlin.com -- | Michael Nazzareno Trimarchi Amarula Solutions BV | | COO - Founder Cruquiuskade 47 | | +31(0)851119172 Amsterdam 1018 AM NL | | [`as] http://www.amarulasolutions.com |
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