From: Venkatesh Yadav Abbarapu <venkatesh.abbar...@xilinx.com>
As per the zc1275 design x1 mode is enabled so changing the
spi-rx-bus-width property to x1.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbar...@xilinx.com>
Signed-off-by: Michal Simek <michal.si...@xilinx.com>
---
arch/arm/dts/zynqmp-zc1275-revB.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/zynqmp-zc1275-revB.dts
b/arch/arm/dts/zynqmp-zc1275-revB.dts
index 027ff83562f8..d7685d2e6d82 100644
--- a/arch/arm/dts/zynqmp-zc1275-revB.dts
+++ b/arch/arm/dts/zynqmp-zc1275-revB.dts
@@ -62,7 +62,7 @@
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <1>;
- spi-rx-bus-width = <4>;
+ spi-rx-bus-width = <1>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@qspi-fsbl-uboot { /* for testing purpose */
label = "qspi-fsbl-uboot";
--
1.9.1
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