The fsl_esdhc driver was for Freescale eSDHC on MPC83XX/MPC85XX
initially. The later QoriQ series processors (which are evolutions
of MPC83XX/MPC85XX) and i.MX series processors were using this
driver for their eSDHCs too.
So there are two evolution directions for eSDHC now. For the two
series processors, the eSDHCs are becoming more and more different.
We should have split it into two drivers, like them
(sdhci-of-esdhc.c/sdhci-esdhc-imx.c) in linux kernel. But it seemed
to be a lot of work now. So let's keep as it is. Be very careful to
change the driver if the changes are not common for all eSDHCs, and
clarify i.MX eSDHC specific things to distingush them with QorIQ
eSDHC.
This patch is to clean up register definition. Besides the QorIQ
eSDHC register definition, the i.MX eSDHC specific registers should
be clarified.
Signed-off-by: Yangbo Lu <yangbo...@nxp.com>
Acked-by: Peng Fan <peng....@nxp.com>
---
Changes for v2:
- Added "Acked-by: Peng Fan".
---
drivers/mmc/fsl_esdhc.c | 66 ++++++-------
include/fsl_esdhc.h | 208 ++++++++++++++++++++++------------------
2 files changed, 149 insertions(+), 125 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index a647bc7f1c..e9622ce9a4 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -54,23 +54,23 @@ struct fsl_esdhc {
uint autoc12err; /* Auto CMD error status register */
uint hostcapblt; /* Host controller capabilities register */
uint wml; /* Watermark level register */
- uint mixctrl; /* For USDHC */
+ uint mixctrl; /* For i.MX USDHC */
char reserved1[4]; /* reserved */
uint fevt; /* Force event register */
uint admaes; /* ADMA error status register */
uint adsaddr; /* ADMA system address register */
char reserved2[4];
- uint dllctrl;
- uint dllstat;
- uint clktunectrlstatus;
+ uint dllctrl; /* For i.MX USDHC */
+ uint dllstat; /* For i.MX USDHC */
+ uint clktunectrlstatus; /* For i.MX USDHC */
char reserved3[4];
- uint strobe_dllctrl;
- uint strobe_dllstat;
+ uint strobe_dllctrl; /* For i.MX USDHC */
+ uint strobe_dllstat; /* For i.MX USDHC */
char reserved4[72];
- uint vendorspec;
- uint mmcboot;
- uint vendorspec2;
- uint tuning_ctrl; /* on i.MX6/7/8 */
+ uint vendorspec; /* For i.MX USDHC */
+ uint mmcboot; /* For i.MX USDHC */
+ uint vendorspec2; /* For i.MX USDHC */
+ uint tuning_ctrl; /* For i.MX USDHC, on i.MX6/7/8 */
char reserved5[44];
uint hostver; /* Host controller version register */
char reserved6[4]; /* reserved */
@@ -80,11 +80,11 @@ struct fsl_esdhc {
char reserved8[4]; /* reserved */
uint hostcapblt2; /* Host controller capabilities register 2 */
char reserved9[8]; /* reserved */
- uint tcr; /* Tuning control register */
+ uint tbctl; /* Tuning block control register */
char reserved10[28]; /* reserved */
uint sddirctl; /* SD direction control register */
char reserved11[712];/* reserved */
- uint scr; /* eSDHC control register */
+ uint esdhcctl; /* eSDHC control register */
};
struct fsl_esdhc_plat {
@@ -496,7 +496,7 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv
*priv, struct mmc *mmc,
/* Switch voltage to 1.8V if CMD11 succeeded */
if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
- esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+ esdhc_setbits32(®s->vendorspec, VENDORSPEC_VSELECT);
printf("Run CMD11 1.8V switch\n");
/* Sleep for 5 ms - max time for card to switch to 1.8V */
@@ -728,23 +728,23 @@ static void esdhc_set_strobe_dll(struct mmc *mmc)
struct fsl_esdhc *regs = priv->esdhc_regs;
u32 val;
- if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
- writel(ESDHC_STROBE_DLL_CTRL_RESET, ®s->strobe_dllctrl);
+ if (priv->clock > STROBE_DLL_CLK_FREQ) {
+ writel(STROBE_DLL_CTRL_RESET, ®s->strobe_dllctrl);
/*
* enable strobe dll ctrl and adjust the delay target
* for the uSDHC loopback read clock
*/
- val = ESDHC_STROBE_DLL_CTRL_ENABLE |
+ val = STROBE_DLL_CTRL_ENABLE |
(priv->strobe_dll_delay_target <<
- ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
+ STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
writel(val, ®s->strobe_dllctrl);
/* wait 1us to make sure strobe dll status register stable */
mdelay(1);
val = readl(®s->strobe_dllstat);
- if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
+ if (!(val & STROBE_DLL_STS_REF_LOCK))
pr_warn("HS400 strobe DLL status REF not lock!\n");
- if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
+ if (!(val & STROBE_DLL_STS_SLV_LOCK))
pr_warn("HS400 strobe DLL status SLV not lock!\n");
}
}
@@ -817,9 +817,9 @@ static int esdhc_set_voltage(struct mmc *mmc)
}
#endif
- esdhc_clrbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+ esdhc_clrbits32(®s->vendorspec, VENDORSPEC_VSELECT);
if (!(esdhc_read32(®s->vendorspec) &
- ESDHC_VENDORSPEC_VSELECT))
+ VENDORSPEC_VSELECT))
return 0;
return -EAGAIN;
@@ -833,8 +833,8 @@ static int esdhc_set_voltage(struct mmc *mmc)
}
}
#endif
- esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
- if (esdhc_read32(®s->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
+ esdhc_setbits32(®s->vendorspec, VENDORSPEC_VSELECT);
+ if (esdhc_read32(®s->vendorspec) & VENDORSPEC_VSELECT)
return 0;
return -EAGAIN;
@@ -952,7 +952,7 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv
*priv, struct mmc *mmc)
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
/* Select to use peripheral clock */
esdhc_clock_control(priv, false);
- esdhc_setbits32(®s->scr, ESDHCCTL_PCS);
+ esdhc_setbits32(®s->esdhcctl, ESDHCCTL_PCS);
esdhc_clock_control(priv, true);
#endif
/* Set the clock speed */
@@ -1028,7 +1028,7 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv,
struct mmc *mmc)
/* Put VEND_SPEC to default value */
if (priv->vs18_enable)
esdhc_write32(®s->vendorspec, (VENDORSPEC_INIT |
- ESDHC_VENDORSPEC_VSELECT));
+ VENDORSPEC_VSELECT));
else
esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
@@ -1038,7 +1038,7 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv,
struct mmc *mmc)
#ifndef ARCH_MXC
/* Enable cache snooping */
- esdhc_write32(®s->scr, 0x00000040);
+ esdhc_write32(®s->esdhcctl, 0x00000040);
#endif
#ifndef CONFIG_FSL_USDHC
@@ -1184,7 +1184,7 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
#endif
if (priv->vs18_enable)
- esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+ esdhc_setbits32(®s->vendorspec, VENDORSPEC_VSELECT);
writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
cfg = &plat->cfg;
@@ -1272,11 +1272,11 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
if (priv->flags & ESDHC_FLAG_STD_TUNING) {
u32 val = readl(®s->tuning_ctrl);
- val |= ESDHC_STD_TUNING_EN;
- val &= ~ESDHC_TUNING_START_TAP_MASK;
+ val |= STD_TUNING_EN;
+ val &= ~TUNING_START_TAP_MASK;
val |= priv->tuning_start_tap;
- val &= ~ESDHC_TUNING_STEP_MASK;
- val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
+ val &= ~TUNING_STEP_MASK;
+ val |= (priv->tuning_step) << TUNING_STEP_SHIFT;
writel(val, ®s->tuning_ctrl);
}
}
@@ -1484,10 +1484,10 @@ static int fsl_esdhc_probe(struct udevice *dev)
val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
priv->tuning_step = val;
val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
- ESDHC_TUNING_START_TAP_DEFAULT);
+ TUNING_START_TAP_DEFAULT);
priv->tuning_start_tap = val;
val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
- ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
+ STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
priv->strobe_dll_delay_target = val;
if (dev_read_bool(dev, "non-removable")) {
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 8dbd5249a7..e693a6244e 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -20,27 +20,87 @@
#include "../board/freescale/common/qixis.h"
#endif
-/* FSL eSDHC-specific constants */
+/*
+ * eSDHC register definition
+ */
+
+/* SDMA system address register */
+#define DSADDR 0x2e000
+
+/* Block attributes register */
+#define BLKATTR 0x2e004
+#define BLKATTR_CNT(x) ((x & 0xffff) << 16)
+#define BLKATTR_SIZE(x) (x & 0x1fff)
+#define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */
+
+/* Command argument register */
+#define CMDARG 0x0002e008
+
+/* Transfer type register */
+#define XFERTYP 0x0002e00c
+#define XFERTYP_CMD(x) ((x & 0x3f) << 24)
+#define XFERTYP_CMDTYP_NORMAL 0x0
+#define XFERTYP_CMDTYP_SUSPEND 0x00400000
+#define XFERTYP_CMDTYP_RESUME 0x00800000
+#define XFERTYP_CMDTYP_ABORT 0x00c00000
+#define XFERTYP_DPSEL 0x00200000
+#define XFERTYP_CICEN 0x00100000
+#define XFERTYP_CCCEN 0x00080000
+#define XFERTYP_RSPTYP_NONE 0
+#define XFERTYP_RSPTYP_136 0x00010000
+#define XFERTYP_RSPTYP_48 0x00020000
+#define XFERTYP_RSPTYP_48_BUSY 0x00030000
+#define XFERTYP_MSBSEL 0x00000020
+#define XFERTYP_DTDSEL 0x00000010
+#define XFERTYP_DDREN 0x00000008
+#define XFERTYP_AC12EN 0x00000004
+#define XFERTYP_BCEN 0x00000002
+#define XFERTYP_DMAEN 0x00000001
+
+/* Command response 0/1/2/3 register */
+#define CMDRSP0 0x2e010
+#define CMDRSP1 0x2e014
+#define CMDRSP2 0x2e018
+#define CMDRSP3 0x2e01c
+
+/* Buffer data port register */
+#define DATPORT 0x2e020
+
+/* Present state register */
+#define PRSSTAT 0x0002e024
+#define PRSSTAT_DAT0 (0x01000000)
+#define PRSSTAT_CLSL (0x00800000)
+#define PRSSTAT_WPSPL (0x00080000)
+#define PRSSTAT_CDPL (0x00040000)
+#define PRSSTAT_CINS (0x00010000)
+#define PRSSTAT_BREN (0x00000800)
+#define PRSSTAT_BWEN (0x00000400)
+#define PRSSTAT_SDSTB (0X00000008)
+#define PRSSTAT_DLA (0x00000004)
+#define PRSSTAT_CICHB (0x00000002)
+#define PRSSTAT_CIDHB (0x00000001)
+
+/* Protocol control register */
+#define PROCTL 0x0002e028
+#define PROCTL_INIT 0x00000020
+#define PROCTL_DTW_4 0x00000002
+#define PROCTL_DTW_8 0x00000004
+#define PROCTL_D3CD 0x00000008
+
+/* Syetem control register */
#define SYSCTL 0x0002e02c
#define SYSCTL_INITA 0x08000000
#define SYSCTL_TIMEOUT_MASK 0x000f0000
#define SYSCTL_CLOCK_MASK 0x0000fff0
-#if !defined(CONFIG_FSL_USDHC)
#define SYSCTL_CKEN 0x00000008
#define SYSCTL_PEREN 0x00000004
#define SYSCTL_HCKEN 0x00000002
#define SYSCTL_IPGEN 0x00000001
-#endif
#define SYSCTL_RSTA 0x01000000
#define SYSCTL_RSTC 0x02000000
#define SYSCTL_RSTD 0x04000000
-#define VENDORSPEC_CKEN 0x00004000
-#define VENDORSPEC_PEREN 0x00002000
-#define VENDORSPEC_HCKEN 0x00001000
-#define VENDORSPEC_IPGEN 0x00000800
-#define VENDORSPEC_INIT 0x20007809
-
+/* Interrupt status register */
#define IRQSTAT 0x0002e030
#define IRQSTAT_DMAE (0x10000000)
#define IRQSTAT_AC12E (0x01000000)
@@ -63,9 +123,10 @@
#define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
#define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \
- IRQSTAT_DMAE)
+ IRQSTAT_DMAE)
#define DATA_COMPLETE (IRQSTAT_TC | IRQSTAT_DINT)
+/* Interrupt status enable register */
#define IRQSTATEN 0x0002e034
#define IRQSTATEN_DMAE (0x10000000)
#define IRQSTATEN_AC12E (0x01000000)
@@ -86,62 +147,15 @@
#define IRQSTATEN_TC (0x00000002)
#define IRQSTATEN_CC (0x00000001)
-#define ESDHCCTL 0x0002e40c
-#define ESDHCCTL_PCS (0x00080000)
-
-#define PRSSTAT 0x0002e024
-#define PRSSTAT_DAT0 (0x01000000)
-#define PRSSTAT_CLSL (0x00800000)
-#define PRSSTAT_WPSPL (0x00080000)
-#define PRSSTAT_CDPL (0x00040000)
-#define PRSSTAT_CINS (0x00010000)
-#define PRSSTAT_BREN (0x00000800)
-#define PRSSTAT_BWEN (0x00000400)
-#define PRSSTAT_SDSTB (0X00000008)
-#define PRSSTAT_DLA (0x00000004)
-#define PRSSTAT_CICHB (0x00000002)
-#define PRSSTAT_CIDHB (0x00000001)
-
-#define PROCTL 0x0002e028
-#define PROCTL_INIT 0x00000020
-#define PROCTL_DTW_4 0x00000002
-#define PROCTL_DTW_8 0x00000004
-#define PROCTL_D3CD 0x00000008
-
-#define CMDARG 0x0002e008
-
-#define XFERTYP 0x0002e00c
-#define XFERTYP_CMD(x) ((x & 0x3f) << 24)
-#define XFERTYP_CMDTYP_NORMAL 0x0
-#define XFERTYP_CMDTYP_SUSPEND 0x00400000
-#define XFERTYP_CMDTYP_RESUME 0x00800000
-#define XFERTYP_CMDTYP_ABORT 0x00c00000
-#define XFERTYP_DPSEL 0x00200000
-#define XFERTYP_CICEN 0x00100000
-#define XFERTYP_CCCEN 0x00080000
-#define XFERTYP_RSPTYP_NONE 0
-#define XFERTYP_RSPTYP_136 0x00010000
-#define XFERTYP_RSPTYP_48 0x00020000
-#define XFERTYP_RSPTYP_48_BUSY 0x00030000
-#define XFERTYP_MSBSEL 0x00000020
-#define XFERTYP_DTDSEL 0x00000010
-#define XFERTYP_DDREN 0x00000008
-#define XFERTYP_AC12EN 0x00000004
-#define XFERTYP_BCEN 0x00000002
-#define XFERTYP_DMAEN 0x00000001
-
-#define CINS_TIMEOUT 1000
-#define PIO_TIMEOUT 500
-
-#define DSADDR 0x2e004
-
-#define CMDRSP0 0x2e010
-#define CMDRSP1 0x2e014
-#define CMDRSP2 0x2e018
-#define CMDRSP3 0x2e01c
-
-#define DATPORT 0x2e020
+/* Host controller capabilities register */
+#define ESDHC_HOSTCAPBLT_VS18 0x04000000
+#define ESDHC_HOSTCAPBLT_VS30 0x02000000
+#define ESDHC_HOSTCAPBLT_VS33 0x01000000
+#define ESDHC_HOSTCAPBLT_SRS 0x00800000
+#define ESDHC_HOSTCAPBLT_DMAS 0x00400000
+#define ESDHC_HOSTCAPBLT_HSS 0x00200000
+/* Watermark level register */
#define WML 0x2e044
#define WML_WRITE 0x00010000
#ifdef CONFIG_FSL_SDHC_V2_3
@@ -160,21 +174,23 @@
#define WML_WR_WML_MASK 0xff0000
#endif
-#define BLKATTR 0x2e004
-#define BLKATTR_CNT(x) ((x & 0xffff) << 16)
-#define BLKATTR_SIZE(x) (x & 0x1fff)
-#define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */
+/* eSDHC control register */
+#define ESDHCCTL 0x0002e40c
+#define ESDHCCTL_PCS (0x00080000)
-#define ESDHC_HOSTCAPBLT_VS18 0x04000000
-#define ESDHC_HOSTCAPBLT_VS30 0x02000000
-#define ESDHC_HOSTCAPBLT_VS33 0x01000000
-#define ESDHC_HOSTCAPBLT_SRS 0x00800000
-#define ESDHC_HOSTCAPBLT_DMAS 0x00400000
-#define ESDHC_HOSTCAPBLT_HSS 0x00200000
+/*
+ * i.MX eSDHC specific register definition
+ */
-#define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */
+/* Vendor specific register */
+#define VENDORSPEC_CKEN 0x00004000
+#define VENDORSPEC_PEREN 0x00002000
+#define VENDORSPEC_HCKEN 0x00001000
+#define VENDORSPEC_IPGEN 0x00000800
+#define VENDORSPEC_INIT 0x20007809
+#define VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */
-/* Imported from Linux Kernel drivers/mmc/host/sdhci-esdhc-imx.c */
+/* Mixer control register */
#define MIX_CTRL_DDREN BIT(3)
#define MIX_CTRL_DTDSEL_READ BIT(4)
#define MIX_CTRL_AC23EN BIT(7)
@@ -189,24 +205,30 @@
/* Tuning bits */
#define MIX_CTRL_TUNING_MASK 0x03c00000
-/* strobe dll register */
-#define ESDHC_STROBE_DLL_CTRL 0x70
-#define ESDHC_STROBE_DLL_CTRL_ENABLE BIT(0)
-#define ESDHC_STROBE_DLL_CTRL_RESET BIT(1)
-#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7
-#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
+/* Strobe dll control register */
+#define STROBE_DLL_CTRL 0x70
+#define STROBE_DLL_CTRL_ENABLE BIT(0)
+#define STROBE_DLL_CTRL_RESET BIT(1)
+#define STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7
+#define STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
-#define ESDHC_STROBE_DLL_STATUS 0x74
-#define ESDHC_STROBE_DLL_STS_REF_LOCK BIT(1)
-#define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1
-#define ESDHC_STROBE_DLL_CLK_FREQ 100000000
+/* Strobe dll status register */
+#define STROBE_DLL_STATUS 0x74
+#define STROBE_DLL_STS_REF_LOCK BIT(1)
+#define STROBE_DLL_STS_SLV_LOCK 0x1
+#define STROBE_DLL_CLK_FREQ 100000000
-#define ESDHC_STD_TUNING_EN BIT(24)
+/* Tuning control register */
+#define STD_TUNING_EN BIT(24)
/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
-#define ESDHC_TUNING_START_TAP_DEFAULT 0x1
-#define ESDHC_TUNING_START_TAP_MASK 0xff
-#define ESDHC_TUNING_STEP_MASK 0x00070000
-#define ESDHC_TUNING_STEP_SHIFT 16
+#define TUNING_START_TAP_DEFAULT 0x1
+#define TUNING_START_TAP_MASK 0xff
+#define TUNING_STEP_MASK 0x00070000
+#define TUNING_STEP_SHIFT 16
+
+/*
+ * Other definition
+ */
#define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
#define ESDHC_FLAG_ENGCM07207 BIT(2)
@@ -220,6 +242,8 @@
#define ESDHC_FLAG_ERR010450 BIT(10)
#define ESDHC_FLAG_HS400_ES BIT(11)
+#define PIO_TIMEOUT 500
+
struct fsl_esdhc_cfg {
phys_addr_t esdhc_base;
u32 sdhc_clk;
--
2.17.1
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