On 2/18/19 12:38 PM, Jagan Teki wrote:
Hi Stefan,
On Fri, Feb 15, 2019 at 12:12 PM Stefan Mavrodiev <ste...@olimex.com> wrote:
[snip]
+static const unsigned long sun4i_spi_bits[] = {
Same here, make it uint32_t, since it describes register masks in 32 bit
registers.
+ [SPI_GCR_TP] = BIT(18),
+ [SPI_TCR_CPHA] = BIT(2),
+ [SPI_TCR_CPOL] = BIT(3),
+ [SPI_TCR_CS_ACTIVE_LOW] = BIT(4),
+ [SPI_TCR_XCH] = BIT(10),
+ [SPI_TCR_CS_SEL] = 12,
+ [SPI_TCR_CS_MASK] = 0x3000,
+ [SPI_TCR_CS_MANUAL] = BIT(16),
+ [SPI_TCR_CS_LEVEL] = BIT(17),
+ [SPI_FCR_TF_RST] = BIT(8),
+ [SPI_FCR_RF_RST] = BIT(9),
+ [SPI_FSR_RF_CNT_MASK] = GENMASK(6, 0),
+};
+
+static const struct sun4i_spi_variant sun4i_a10_spi_variant = {
+ .regs = sun4i_spi_regs,
+ .bits = sun4i_spi_bits,
+};
+
static const struct udevice_id sun4i_spi_ids[] = {
- { .compatible = "allwinner,sun4i-a10-spi" },
+ {
+ .compatible = "allwinner,sun4i-a10-spi",
+ .data = (ulong)&sun4i_a10_spi_variant,
+ },
{ }
};
I checked the rest as good as my brain allows me at 11pm, but it's still
quite a change with a lot of bits here and there :-(
Stefan, can you please test that this still works for you on the A20? If
I find some time I can try to hook up some SPI chip to my BananaPi, but
I guess it's easier for you to test.
Here are some test results:
=> sf probe 0:0
SF: Detected w25q128 with page size 256 Bytes, erase size 4 KiB, total
16 MiB
=> sf test 0 100000
SPI flash test:
0 erase: 11363 ticks, 90 KiB/s 0.720 Mbps
1 check: 825 ticks, 1241 KiB/s 9.928 Mbps
2 write: 2472 ticks, 414 KiB/s 3.312 Mbps
3 read: 815 ticks, 1256 KiB/s 10.048 Mbps
Test passed
0 erase: 11363 ticks, 90 KiB/s 0.720 Mbps
1 check: 825 ticks, 1241 KiB/s 9.928 Mbps
2 write: 2472 ticks, 414 KiB/s 3.312 Mbps
3 read: 815 ticks, 1256 KiB/s 10.048 Mbps
The original tests can be seen here [1].
Apparently the patch works and it can be seen some
speed improvement.
Thanks for testing this.
Can I add your Tested-by credit?
Sure.
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