On 02/10/2019 05:17 PM, Andre Przywara wrote:
The timing registers in the DRAM controller can be programmed in any
order, as they will only take effect once the controller is eventually
"activated".
Switch the MMIO writes in mctl_set_timing_lpddr3() over to use
writel_relaxed(), since we don't need the stronger guarantee of the
normal writel(). We satisfy the overall ordering requirement by ending
the function with an explicit DMB barrier.
In this case we are not interested in the performance benefit this
usually gives, but in the saved instructions, which sum up for the many
writes we have in the timing setup.
Due to alignment effects this shrinks our chronically tight H6 SPL by a
whopping 2KB, which brings it in the same region as for the other
AArch64 Allwinner SPL builds.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
If you say it still works, it sounds like a pretty nifty optimization :).
Reviewed-by: Alexander Graf <ag...@suse.de>
Alex
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