The comment about SPL memory layout for socfpga gen5 is outdated: the initial malloc memory is now at the end of the SRAM, gd is below it (see board_init_f_alloc_reserve).
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschm...@gmail.com> --- include/configs/socfpga_common.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index c9cbf8f5e3..a3fbca0a5d 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -237,9 +237,9 @@ unsigned int cm_get_qspi_controller_clk_hz(void); * * 0xFFFF_0000 ...... Start of SRAM * 0xFFFF_xxxx ...... Top of stack (grows down) - * 0xFFFF_yyyy ...... Malloc area - * 0xFFFF_zzzz ...... Global Data - * 0xFFFF_FF00 ...... End of SRAM + * 0xFFFF_yyyy ...... Global Data + * 0xFFFF_zzzz ...... Malloc area + * 0xFFFF_FFFF ...... End of SRAM * * SRAM Memory layout for Arria 10: * 0xFFE0_0000 ...... Start of SRAM (bottom) -- 2.17.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot