Expand the commit log to describe this new part. Include a URL reference to where it can be reviewed.
Vipin KUMAR wrote: > Signed-off-by: Vipin Kumar <vipin.ku...@st.com> > --- > arch/arm/cpu/arm_cortexa8/spear13xx/Makefile | 52 ++++ > arch/arm/cpu/arm_cortexa8/spear13xx/cache.S | 112 ++++++++ > arch/arm/cpu/arm_cortexa8/spear13xx/cpu.c | 99 +++++++ > arch/arm/cpu/arm_cortexa8/spear13xx/reset.c | 47 ++++ > arch/arm/cpu/arm_cortexa8/spear13xx/timer.c | 136 ++++++++++ > arch/arm/include/asm/arch-spear13xx/hardware.h | 40 +++ > arch/arm/include/asm/arch-spear13xx/spr_gpt.h | 85 ++++++ > arch/arm/include/asm/arch-spear13xx/spr_misc.h | 317 > +++++++++++++++++++++++ > arch/arm/include/asm/arch-spear13xx/sys_proto.h | 32 +++ > 9 files changed, 920 insertions(+), 0 deletions(-) > create mode 100644 arch/arm/cpu/arm_cortexa8/spear13xx/Makefile > create mode 100644 arch/arm/cpu/arm_cortexa8/spear13xx/cache.S > create mode 100644 arch/arm/cpu/arm_cortexa8/spear13xx/cpu.c > create mode 100755 arch/arm/cpu/arm_cortexa8/spear13xx/reset.c > create mode 100644 arch/arm/cpu/arm_cortexa8/spear13xx/timer.c > create mode 100644 arch/arm/include/asm/arch-spear13xx/hardware.h > create mode 100644 arch/arm/include/asm/arch-spear13xx/spr_gpt.h > create mode 100644 arch/arm/include/asm/arch-spear13xx/spr_misc.h > create mode 100644 arch/arm/include/asm/arch-spear13xx/sys_proto.h > > diff --git a/arch/arm/cpu/arm_cortexa8/spear13xx/Makefile > b/arch/arm/cpu/arm_cortexa8/spear13xx/Makefile > new file mode 100644 > index 0000000..4157164 > --- /dev/null > +++ b/arch/arm/cpu/arm_cortexa8/spear13xx/Makefile > @@ -0,0 +1,52 @@ > +# > +# (C) Copyright 2000-2003 > +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. > +# > +# (C) Copyright 2008 > +# Guennadi Liakhovetki, DENX Software Engineering, <l...@denx.de> > +# > +# See file CREDITS for list of people who contributed to this > +# project. > +# > +# This program is free software; you can redistribute it and/or > +# modify it under the terms of the GNU General Public License as > +# published by the Free Software Foundation; either version 2 of > +# the License, or (at your option) any later version. > +# > +# This program is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > +# You should have received a copy of the GNU General Public License > +# along with this program; if not, write to the Free Software > +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, > +# MA 02111-1307 USA > +# > + > +include $(TOPDIR)/config.mk > + > +LIB = $(obj)lib$(SOC).a > + > +COBJS += timer.o > +COBJS += reset.o > +COBJS += cpu.o > + > +SOBJS = cache.o > + > +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) > +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) > + > +all: $(obj).depend $(LIB) > + > +$(LIB): $(OBJS) > + $(AR) $(ARFLAGS) $@ $(OBJS) > + > +######################################################################### > + > +# defines $(obj).depend target > +include $(SRCTREE)/rules.mk > + > +sinclude $(obj).depend > + > +######################################################################### > diff --git a/arch/arm/cpu/arm_cortexa8/spear13xx/cache.S > b/arch/arm/cpu/arm_cortexa8/spear13xx/cache.S > new file mode 100644 > index 0000000..b3d1fb0 > --- /dev/null > +++ b/arch/arm/cpu/arm_cortexa8/spear13xx/cache.S > @@ -0,0 +1,112 @@ > +/* > + * (C) Copyright 2009 > + * Vipin Kumar, ST Micoelectronics, vipin.ku...@st.com. > + * > + * See file CREDITS for list of people who contributed to this > + * project. This cache.S is extremely similar to s5pc1xx/cache.S And to a lesser degree the omap3/cache.S. When a work is based on another work, the original work MUST be acknowledged. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +.global invalidate_dcache > + > +/* > + * invalidate_dcache() > + * > + * Invalidate the whole D-cache. > + * > + * Corrupted registers: r0-r5, r7, r9-r11 > + * > + * - mm - mm_struct describing address space > + */ > +invalidate_dcache: > + stmfd r13!, {r0 - r5, r7, r9 - r12, r14} > + > + mrc p15, 1, r0, c0, c0, 1 @ read clidr > + ands r3, r0, #0x7000000 @ extract loc from clidr > + mov r3, r3, lsr #23 @ left align loc bit field > + beq finished_inval @ if loc is 0, then no need to > + @ clean > + mov r10, #0 @ start clean at cache level 0 > +inval_loop1: > + add r2, r10, r10, lsr #1 @ work out 3x current cache > + @ level > + mov r1, r0, lsr r2 @ extract cache type bits from > + @ clidr > + and r1, r1, #7 @ mask of the bits for current > + @ cache only > + cmp r1, #2 @ see what cache we have at > + @ this level > + blt skip_inval @ skip if no cache, or just > + @ i-cache > + mcr p15, 2, r10, c0, c0, 0 @ select current cache level > + @ in cssr > + mov r2, #0 @ operand for mcr SBZ > + mcr p15, 0, r2, c7, c5, 4 @ flush prefetch buffer to > + @ sych the new cssr&csidr, > + @ with armv7 this is 'isb', > + @ but we compile with armv5 > + mrc p15, 1, r1, c0, c0, 0 @ read the new csidr > + and r2, r1, #7 @ extract the length of the > + @ cache lines > + add r2, r2, #4 @ add 4 (line length offset) > + ldr r4, =0x3ff > + ands r4, r4, r1, lsr #3 @ find maximum number on the > + @ way size > + clz r5, r4 @ find bit position of way > + @ size increment > + ldr r7, =0x7fff > + ands r7, r7, r1, lsr #13 @ extract max number of the > + @ index size > +inval_loop2: > + mov r9, r4 @ create working copy of max > + @ way size > +inval_loop3: > + orr r11, r10, r9, lsl r5 @ factor way and cache number > + @ into r11 > + orr r11, r11, r7, lsl r2 @ factor index number into r11 > + mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way > + subs r9, r9, #1 @ decrement the way > + bge inval_loop3 > + subs r7, r7, #1 @ decrement the index > + bge inval_loop2 > +skip_inval: > + add r10, r10, #2 @ increment cache number > + cmp r3, r10 > + bgt inval_loop1 > +finished_inval: > + mov r10, #0 @ swith back to cache level 0 > + mcr p15, 2, r10, c0, c0, 0 @ select current cache level > + @ in cssr > + mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer, > + @ with armv7 this is 'isb', > + @ but we compile with armv5 > + > + ldmfd r13!, {r0 - r5, r7, r9 - r12, pc} > + > +.global l2_cache_enable > +/* > + * l2_cache_enable > + */ > +l2_cache_enable: > + bx r14 > + > +.global l2_cache_disable > +/* > + * l2_cache_disable > + */ > +l2_cache_disable: > + bx r14 > diff --git a/arch/arm/cpu/arm_cortexa8/spear13xx/cpu.c > b/arch/arm/cpu/arm_cortexa8/spear13xx/cpu.c > new file mode 100644 > index 0000000..5a0ae56 > --- /dev/null > +++ b/arch/arm/cpu/arm_cortexa8/spear13xx/cpu.c > @@ -0,0 +1,99 @@ > +/* > + * (C) Copyright 2009 > + * Vipin Kumar, ST Micoelectronics, vipin.ku...@st.com. > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#include <common.h> > +#include <asm/io.h> > +#include <asm/arch/hardware.h> > +#include <asm/arch/spr_misc.h> > + > +u32 get_device_type(void) > +{ > + return 0; > +} > + This is needed for omap3. Remove > +#ifdef CONFIG_ARCH_CPU_INIT > +int arch_cpu_init(void) > +{ > + struct misc_regs *const misc_p = > + (struct misc_regs *)CONFIG_SPEAR_MISCBASE; > + u32 perip1_clk_enb, perip2_clk_enb; > +#if defined(CONFIG_NAND_FSMC) > + u32 fsmc_cfg; > +#endif > + perip1_clk_enb = readl(&misc_p->perip1_clk_enb); > + perip2_clk_enb = readl(&misc_p->perip2_clk_enb); > + > + perip1_clk_enb |= GPT1_CLKEN; > + > +#if defined(CONFIG_PL011_SERIAL) > + perip1_clk_enb |= UART_CLKEN; > +#endif > + > +#if defined(CONFIG_DESIGNWARE_ETH) > + /* writel(SYNT_CLK_ENB | SYNT_FIN_FULL | SYNT_X_1 | SYNT_Y_5, > + &misc_p->gmac_clk_synt); */ This is dead code Remove. > + writel(PHY_IF_GMII | CLK_SEL_OSCI3, &misc_p->gmac_clk_cfg); > + > + perip1_clk_enb |= GETH_CLKEN; > +#endif > + > +#if defined(CONFIG_DW_UDC) > + perip1_clk_enb |= UDC_UPD_CLKEN; > +#endif > + > +#if defined(CONFIG_DW_I2C) > + perip1_clk_enb |= I2C_CLKEN; > +#endif > + > +#if defined(CONFIG_ST_SMI) > + perip1_clk_enb |= SMI_CLKEN; > +#endif > + > +#if defined(CONFIG_NAND_FSMC) > + fsmc_cfg = readl(&misc_p->fsmc_cfg); > + fsmc_cfg &= ~DEV_SEL_MSK; > + fsmc_cfg |= DEV_SEL_NAND; > +#if defined(CONFIG_BOARD_NAND_16BIT) > + fsmc_cfg |= DEV_WIDTH_16; Similar 16BIT is never defined. Remove dead code > +#elif defined(CONFIG_BOARD_NAND_8BIT) > + fsmc_cfg |= DEV_WIDTH_8; > +#endif > + writel(fsmc_cfg, &misc_p->fsmc_cfg); > + > + perip1_clk_enb |= FSMC_CLKEN; > +#endif > + > + writel(perip1_clk_enb, &misc_p->perip1_clk_enb); > + writel(perip2_clk_enb, &misc_p->perip2_clk_enb); > + > + return 0; > +} > +#endif > + > +#ifdef CONFIG_DISPLAY_CPUINFO > +int print_cpuinfo(void) > +{ > + printf("CPU: SPEAr1300\n"); > + return 0; > +} > +#endif > diff --git a/arch/arm/cpu/arm_cortexa8/spear13xx/reset.c > b/arch/arm/cpu/arm_cortexa8/spear13xx/reset.c > new file mode 100755 > index 0000000..9a43f85 > --- /dev/null > +++ b/arch/arm/cpu/arm_cortexa8/spear13xx/reset.c > @@ -0,0 +1,47 @@ > +/* > + * (C) Copyright 2009 > + * Vipin Kumar, ST Micoelectronics, vipin.ku...@st.com. > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#include <common.h> > +#include <asm/io.h> > +#include <asm/arch/hardware.h> > +#include <asm/arch/spr_misc.h> > + > +void reset_cpu(ulong ignored) > +{ > + struct misc_regs *misc_regs_p = > + (struct misc_regs *)CONFIG_SPEAR_MISCBASE; > + > + printf("System is going to reboot ...\n"); > + > + /* > + * This 1 second delay will allow the above message > + * to be printed before reset > + */ > + udelay((1000 * 1000)); > + > + writel(0x01, &misc_regs_p->sys_sw_res); > + > + /* system will restart */ > + while (1) > + ; > +} > diff --git a/arch/arm/cpu/arm_cortexa8/spear13xx/timer.c > b/arch/arm/cpu/arm_cortexa8/spear13xx/timer.c > new file mode 100644 > index 0000000..d114a4a > --- /dev/null > +++ b/arch/arm/cpu/arm_cortexa8/spear13xx/timer.c > @@ -0,0 +1,136 @@ > +/* > + * (C) Copyright 2009 > + * Vipin Kumar, ST Micoelectronics, vipin.ku...@st.com. > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * Looks like this was based on ../arm926ejs/spear/timer.c Please state this even if you are the author of both > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#include <common.h> > +#include <asm/io.h> > +#include <asm/arch/hardware.h> > +#include <asm/arch/spr_gpt.h> > +#include <asm/arch/spr_misc.h> > + > +#define GPT_TICKS (CONFIG_SPEAR_HZ_CLOCK / (1 << prescaler)) > +#define GPT_RESOLUTION (GPT_TICKS / CONFIG_SPEAR_HZ) > +#define READ_TIMER() (readl(&gpt_regs_p->count) & GPT_FREE_RUNNING) > + > +static struct gpt_regs *const gpt_regs_p = > + (struct gpt_regs *)CONFIG_SPEAR_TIMERBASE; > + > +static ulong timestamp; > +static ulong lastdec; > +static const u32 prescaler = GPT_PRESCALER_16; > + > +int timer_init(void) > +{ > + /* disable timers */ > + writel(prescaler | GPT_MODE_AUTO_RELOAD, &gpt_regs_p->control); > + > + /* load value for free running */ > + writel(GPT_FREE_RUNNING, &gpt_regs_p->compare); > + > + /* auto reload, start timer */ > + writel(readl(&gpt_regs_p->control) | GPT_ENABLE, &gpt_regs_p->control); > + > + reset_timer_masked(); > + > + return 0; > +} > + > +/* > + * timer without interrupts > + */ > + > +void reset_timer(void) > +{ > + reset_timer_masked(); > +} > + > +ulong get_timer(ulong base) > +{ > + return (get_timer_masked() / GPT_RESOLUTION) - base; > +} > + > +void set_timer(ulong t) > +{ > + timestamp = t; > +} > + > +void __udelay(unsigned long usec) > +{ > + ulong tmo; > + ulong start = get_timer_masked(); > + ulong tenudelcnt = GPT_TICKS / (1000 * 100); Expand this variable name so it means something. This is a concatenation of abbreviations May consider using unsigned long long if exceeding 32 bits > + ulong rndoff; > + > + rndoff = (usec % 10) ? 1 : 0; > + > + /* tenudelcnt timer tick gives 10 microsecconds delay */ > + tmo = ((usec / 10) + rndoff) * tenudelcnt; > + > + while ((ulong) (get_timer_masked() - start) < tmo) > + ; > +} > + > +void reset_timer_masked(void) > +{ > + /* reset time */ > + lastdec = READ_TIMER(); > + timestamp = 0; > +} > + > +ulong get_timer_masked(void) > +{ > + ulong now = READ_TIMER(); > + > + if (now >= lastdec) { > + /* normal mode */ > + timestamp += now - lastdec; > + } else { > + /* we have an overflow ... */ > + timestamp += now + GPT_FREE_RUNNING - lastdec; > + } > + lastdec = now; > + > + return timestamp; > +} > + > +void udelay_masked(unsigned long usec) > +{ > + return udelay(usec); > +} > + > +/* > + * This function is derived from PowerPC code (read timebase as long long). > + * On ARM it just returns the timer value. > + */ > +unsigned long long get_ticks(void) > +{ > + return get_timer(0); > +} > + > +/* > + * This function is derived from PowerPC code (timebase clock frequency). > + * On ARM it returns the number of timer ticks per second. > + */ > +ulong get_tbclk(void) > +{ > + return CONFIG_SPEAR_HZ; > +} > diff --git a/arch/arm/include/asm/arch-spear13xx/hardware.h > b/arch/arm/include/asm/arch-spear13xx/hardware.h > new file mode 100644 > index 0000000..384260a > --- /dev/null > +++ b/arch/arm/include/asm/arch-spear13xx/hardware.h > @@ -0,0 +1,40 @@ > +/* > + * (C) Copyright 2009 > + * Vipin Kumar, STMicroelectronics, <vipin.ku...@st.com> > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#ifndef _ASM_ARCH_HARDWARE_H > +#define _ASM_ARCH_HARDWARE_H Change this to something non generic with SPEAR13XX in it somewhere. > + > +#define CONFIG_SYS_USBD_BASE (0xE1100000) > +#define CONFIG_SYS_PLUG_BASE (0xE1200000) > +#define CONFIG_SYS_FIFO_BASE (0xE1000800) > +#define CONFIG_SYS_SMI_BASE (0xFC000000) > +#define CONFIG_SPEAR_TIMERBASE (0xE0380000) > +#define CONFIG_SPEAR_MISCBASE (0xE0700000) > +#define CONFIG_SYS_I2C_BASE (0xE0280000) > +#define CONFIG_SPEAR_ETHBASE (0xE2000000) > +#define CONFIG_SYS_FSMC_BASE (0xB0000000) > + > +#define CONFIG_SYS_NAND_CLE (1 << 16) > +#define CONFIG_SYS_NAND_ALE (1 << 17) > + > +#endif /* _ASM_ARCH_HARDWARE_H */ > diff --git a/arch/arm/include/asm/arch-spear13xx/spr_gpt.h > b/arch/arm/include/asm/arch-spear13xx/spr_gpt.h > new file mode 100644 > index 0000000..ad464cb > --- /dev/null > +++ b/arch/arm/include/asm/arch-spear13xx/spr_gpt.h > @@ -0,0 +1,85 @@ > +/* > + * (C) Copyright 2009 > + * Vipin Kumar, ST Micoelectronics, vipin.ku...@st.com. > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#ifndef _SPR_GPT_H > +#define _SPR_GPT_H > + > +struct gpt_regs { > + u8 reserved[0x80]; > + u32 control; > + u32 status; > + u32 compare; > + u32 count; > + u32 capture_re; > + u32 capture_fe; > +}; > + > +/* > + * TIMER_CONTROL register settings > + */ > + > +#define GPT_PRESCALER_MASK 0x000F > +#define GPT_PRESCALER_1 0x0000 > +#define GPT_PRESCALER_2 0x0001 > +#define GPT_PRESCALER_4 0x0002 > +#define GPT_PRESCALER_8 0x0003 > +#define GPT_PRESCALER_16 0x0004 > +#define GPT_PRESCALER_32 0x0005 > +#define GPT_PRESCALER_64 0x0006 > +#define GPT_PRESCALER_128 0x0007 > +#define GPT_PRESCALER_256 0x0008 > + > +#define GPT_MODE_SINGLE_SHOT 0x0010 > +#define GPT_MODE_AUTO_RELOAD 0x0000 > + > +#define GPT_ENABLE 0x0020 > + > +#define GPT_CAPT_MODE_MASK 0x00C0 > +#define GPT_CAPT_MODE_NONE 0x0000 > +#define GPT_CAPT_MODE_RE 0x0040 > +#define GPT_CAPT_MODE_FE 0x0080 > +#define GPT_CAPT_MODE_BOTH 0x00C0 > + > +#define GPT_INT_MATCH 0x0100 > +#define GPT_INT_FE 0x0200 > +#define GPT_INT_RE 0x0400 > + > +/* > + * TIMER_STATUS register settings > + */ > + > +#define GPT_STS_MATCH 0x0001 > +#define GPT_STS_FE 0x0002 > +#define GPT_STS_RE 0x0004 > + > +/* > + * TIMER_COMPARE register settings > + */ > + > +#define GPT_FREE_RUNNING 0xFFFF > + > +/* Timer, HZ specific defines */ > +#define CONFIG_SPEAR_HZ (1000) > +#define CONFIG_SPEAR_HZ_CLOCK (24000000) > + > +#endif > diff --git a/arch/arm/include/asm/arch-spear13xx/spr_misc.h > b/arch/arm/include/asm/arch-spear13xx/spr_misc.h > new file mode 100644 > index 0000000..0b24843 > --- /dev/null > +++ b/arch/arm/include/asm/arch-spear13xx/spr_misc.h > @@ -0,0 +1,317 @@ > +/* > + * (C) Copyright 2000-2009 > + * Vipin Kumar, ST Microelectronics, vipin.ku...@st.com > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#ifndef __SPR13XX_MISC_H > +#define __SPR13XX_MISC_H > + > +struct misc_regs { > + u32 soc_cfg; /* 0x000 */ > + u32 bootstrap_cfg; /* 0x004 */ > + u8 reserved_1[0x100 - 0x8]; > + u32 pcm_cfg; /* 0x100 */ > + u32 pcm_wkup_cfg; /* 0x104 */ > + u32 switch_ctr; /* 0x108 */ > + u8 reserved_2[0x200 - 0x10c]; > + u32 sys_clk_ctrl; /* 0x200 */ > + u32 sys_sw_res; /* 0x204 */ > + u32 sys_clk_plltimer; /* 0x208 */ > + u32 sys_clk_oscitimer; /* 0x20c */ > + u32 pll_cfg; /* 0x210 */ > + u32 pll1_ctr; /* 0x214 */ > + u32 pll1_frq; /* 0x218 */ > + u32 pll1_mod; /* 0x21c */ > + u32 pll2_ctr; /* 0x220 */ > + u32 pll2_frq; /* 0x224 */ > + u32 pll2_mod; /* 0x228 */ > + u32 pll3_ctr; /* 0x22c */ > + u32 pll3_frq; /* 0x230 */ > + u32 pll3_mod; /* 0x234 */ > + u32 pll4_ctr; /* 0x238 */ > + u32 pll4_frq; /* 0x23C */ > + u32 pll4_mod; /* 0x240 */ > + u32 perip_clk_cfg; /* 0x244 */ > + u32 gmac_clk_cfg; /* 0x248 */ > + u32 c3_clk_synt; /* 0x24c */ > + u32 clcd_clk_synt; /* 0x250 */ > + u32 uart_clk_synt; /* 0x254 */ > + u32 gmac_clk_synt; /* 0x258 */ > + u32 mcif_sd_clk_synt; /* 0x25c */ > + u32 mcif_cfxd_clk_synt; /* 0x260 */ > + u32 ras_clk_synt0; /* 0x264 */ > + u32 ras_clk_synt1; /* 0x268 */ > + u32 ras_clk_synt2; /* 0x26c */ > + u32 ras_clk_synt3; /* 0x270 */ > + u32 perip1_clk_enb; /* 0x274 */ > + u32 perip2_clk_enb; /* 0x278 */ > + u32 perip1_sw_rst; /* 0x27c */ > + u32 perip2_sw_rst; /* 0x280 */ > + u32 ras_clk_enb; /* 0x284 */ > + u32 ras_sw_rst; /* 0x288 */ > + u32 pll1_synt; /* 0x28c */ > + u32 i2s_clk_cfg; /* 0x290 */ > + u8 reserved_3[0x300 - 0x294]; > + u32 dmac_hs_sel; /* 0x300 */ > + u32 dmac_sel; /* 0x304 */ > + u32 dmac_flow_sel; /* 0x308 */ > + u32 dmac_dir_sel; /* 0x30c */ > + u32 dmac_cfg; /* 0x310 */ > + u32 usbphy_gen_cfg; /* 0x314 */ > + u32 usbphy_p1_cfg; /* 0x318 */ > + u32 usbphy_p2_cfg; /* 0x31c */ > + u32 usbphy_p3_cfg; /* 0x320 */ > + u32 pcie_cfg; /* 0x324 */ > + u32 pcie_miphy_cfg; /* 0x328 */ > + u32 perip_cfg; /* 0x32c */ > + u32 fsmc_cfg; /* 0x330 */ > + u32 mpmc_ctr_sts; /* 0x334 */ > + u8 reserved_4[0x400 - 0x338]; > + u32 expi_clk_cfg; /* 0x400 */ > + u32 expi_cfg; /* 0x404 */ > + u32 expi_dmachs_flex; /* 0x408 */ > + u8 reserved_5[0x500 - 0x40C]; > + u32 prc1_lock_ctr; /* 0x500 */ > + u32 prc2_lock_ctr; /* 0x504 */ > + u32 prc1_irq_ctr; /* 0x508 */ > + u8 reserved_6[0x51c - 0x50c]; > + u32 prc2_irq_ctr; /* 0x51c */ > + u8 reserved_7[0x600 - 0x520]; > + u32 pad_pu_cfg_1; /* 0x600 */ > + u32 pad_pu_cfg_2; /* 0x604 */ > + u32 pad_pu_cfg_3; /* 0x608 */ > + u32 pad_pu_cfg_4; /* 0x60c */ > + u32 pad_pu_cfg_5; /* 0x610 */ > + u32 pad_pu_cfg_6; /* 0x614 */ > + u32 pad_pu_cfg_7; /* 0x618 */ > + u32 pad_pu_cfg_8; /* 0x61c */ > + u32 pad_pd_cfg_1; /* 0x620 */ > + u32 pad_pd_cfg_2; /* 0x624 */ > + u32 pad_pd_cfg_3; /* 0x628 */ > + u32 pad_pd_cfg_4; /* 0x62c */ > + u32 pad_pd_cfg_5; /* 0x630 */ > + u32 pad_pd_cfg_6; /* 0x634 */ > + u32 pad_pd_cfg_7; /* 0x638 */ > + u32 pad_pd_cfg_8; /* 0x63c */ > + u32 pad_sleep_cfg; /* 0x640 */ > + u32 pad_hyst_cfg; /* 0x644 */ > + u32 pad_drv_cfg; /* 0x648 */ > + u32 pad_slew_cfg; /* 0x64c */ > + u32 pad_function_en_1; /* 0x650 */ > + u32 pad_function_en_2; /* 0x654 */ > + u32 pad_function_en_3; /* 0x658 */ > + u32 ddr_pad_cfg; /* 0x65c */ > + u8 reserved_8[0x6C4 - 0x660]; > + u32 thsens_cfg; /* 0x6C4 */ > + u8 reserved_9[0x700 - 0x6C8]; > + u32 comp_1_cfg; /* 0x700 */ > + u32 comp_2_cfg; /* 0x704 */ > + u32 comp3v3_1_cfg; /* 0x708 */ > + u32 comp3v3_2_cfg; /* 0x70c */ > + u32 compddr_cfg; /* 0x710 */ > + u8 reserved_10[0x800 - 0x714]; > + u32 otp_prog_ctr; /* 0x800 */ > + u32 otp_wdata1_1; /* 0x804 */ > + u32 otp_wdata1_2; /* 0x808 */ > + u32 otp_wdata1_3; /* 0x80c */ > + u32 otp_wdata1_4; /* 0x810 */ > + u32 otp_wdata1_5; /* 0x814 */ > + u32 otp_wdata1_6; /* 0x818 */ > + u32 otp_wdata1_7; /* 0x81c */ > + u32 otp_wdata1_8; /* 0x820 */ > + u32 otp_wdata2_1; /* 0x824 */ > + u32 otp_wdata2_2; /* 0x828 */ > + u32 otp_wdata2_3; /* 0x82c */ > + u32 otp_wdata2_4; /* 0x830 */ > + u32 otp_wdata2_5; /* 0x834 */ > + u32 otp_wdata2_6; /* 0x838 */ > + u32 otp_wdata2_7; /* 0x83c */ > + u32 otp_wdata2_8; /* 0x840 */ > + u32 otp_mask_1; /* 0x844 */ > + u32 otp_mask_2; /* 0x848 */ > + u32 otp_mask_3; /* 0x84c */ > + u32 otp_mask_4; /* 0x850 */ > + u32 otp_mask_5; /* 0x854 */ > + u32 otp_mask_6; /* 0x858 */ > + u32 otp_mask_7; /* 0x85c */ > + u32 otp_mask_8; /* 0x860 */ > + u32 otp_rdata1_1; /* 0x864 */ > + u32 otp_rdata1_2; /* 0x868 */ > + u32 otp_rdata1_3; /* 0x86c */ > + u32 otp_rdata1_4; /* 0x870 */ > + u32 otp_rdata1_5; /* 0x874 */ > + u32 otp_rdata1_6; /* 0x878 */ > + u32 otp_rdata1_7; /* 0x87c */ > + u32 otp_rdata1_8; /* 0x880 */ > + u32 otp_rdata2_1; /* 0x884 */ > + u32 otp_rdata2_2; /* 0x888 */ > + u32 otp_rdata2_3; /* 0x88c */ > + u32 otp_rdata2_4; /* 0x890 */ > + u32 otp_rdata2_5; /* 0x894 */ > + u32 otp_rdata2_6; /* 0x898 */ > + u32 otp_rdata2_7; /* 0x89c */ > + u32 otp_rdata2_8; /* 0x8a0 */ > + u32 otp_rdatam_1; /* 0x8a4 */ > + u32 otp_rdatam_2; /* 0x8a8 */ > + u32 otp_rdatam_3; /* 0x8ac */ > + u32 otp_rdatam_4; /* 0x8b0 */ > + u32 otp_rdatam_5; /* 0x8b4 */ > + u32 otp_rdatam_6; /* 0x8b8 */ > + u32 otp_rdatam_7; /* 0x8bc */ > + u32 otp_rdatam_8; /* 0x8c0 */ > + u8 reserved_11[0x900 - 0x8c4]; > + u32 a9sm_clusterid; /* 0x900 */ > + u32 a9sm_status; /* 0x904 */ > + u32 a9sm_debug; /* 0x908 */ > + u32 a9sm_filter; /* 0x90c */ > + u32 a9sm_parity_cfg; /* 0x910 */ > + u32 a9sm_parity_err; /* 0x914 */ > + u8 reserved_12[0xa00 - 0x918]; > + u32 die_id_1; /* 0xa00 */ > + u32 die_id_2; /* 0xa04 */ > + u32 die_id_3; /* 0xa08 */ > + u32 die_id_4; /* 0xa0c */ > + u32 die_id_valid; /* 0xa10 */ > + u8 reserved_13[0xb00 - 0xa14]; > + u32 ras1_gpp_inp; /* 0xb00 */ > + u32 ras2_gpp_inp; /* 0xb04 */ > + u32 ras1_gpp_out; /* 0xb08 */ > + u32 ras2_gpp_out; /* 0xb0c */ > + u8 reserved_14[0x1000 - 0xb10]; > + u32 miphy_test; /* 0x1000 */ > + u32 pcie_mstr_p1; /* 0x1004 */ > + u32 pcie_awmisc_p1; /* 0x1008 */ > + u32 pcie_armisc_p1; /* 0x100c */ > + u32 pcie_mstr_p2; /* 0x1010 */ > + u32 pcie_awmisc_p2; /* 0x1014 */ > + u32 pcie_armisc_p2; /* 0x1018 */ > + u32 pcie_mstr_p3; /* 0x101c */ > + u32 pcie_awmisc_p3; /* 0x1020 */ > + u32 pcie_armisc_p3; /* 0x1024 */ > +}; > + > +/* sys_clk_ctrl definitions */ > +#define SYS_MODE_MASK (7 << 0) > +#define SYS_MODE_REQ_DOZE (1 << 0) > +#define SYS_MODE_REQ_SLOW (2 << 0) > +#define SYS_MODE_REQ_NORMAL (4 << 0) > +#define PLL_TIMEOUT_ENB (1 << 3) > +#define XTAL_TIMEOUT_ENB (1 << 4) > +#define SYS_STATE_MASK (0xF << 16) > +#define SYS_STATE_NORMAL (0xF << 16) > + > +/* sys_clk_*timer definitions */ > +#define PLL_TIM (0xff << 3) > +#define OSCI_TIM (0xff << 3) > + > +/* pll_freq definitions in MHz */ > +#define FREQ_1000 (0xFA000106) > +#define FREQ_996 (0x53000004) > +#define FREQ_332 (0x53000203) > + > +/* pll_ctr definitions */ > +#define PLLLOCK (1 << 0) > +#define PLLENABLE (1 << 1) > + > +/* perip_clk_cfg definitions */ > +#define MPMC_CLK_PLL4 (1 << 10) > + > +/* perip*_[clk_enb/sw_rst] definitions */ > +#define BUS_CLKEN (1 << 0) /* perip1 */ > +#define SYSROM_CLKEN (1 << 1) > +#define AORAM_CLKEN (1 << 2) > +#define SYSRAM_CLKEN (1 << 3) > +#define FSMC_CLKEN (1 << 4) > +#define SMI_CLKEN (1 << 5) > +#define SD_CLKEN (1 << 6) > +#define CFXD_CLKEN (1 << 7) > +#define GETH_CLKEN (1 << 8) > +#define UHC1_CLKEN (1 << 9) > +#define UHC2_CLKEN (1 << 10) > +#define UDC_UPD_CLKEN (1 << 11) > +#define PCI1_CLKEN (1 << 12) > +#define PCI2_CLKEN (1 << 13) > +#define PCI3_CLKEN (1 << 14) > +#define UART_CLKEN (1 << 15) > +#define SSP_CLKEN (1 << 17) > +#define I2C_CLKEN (1 << 18) > +#define I2S_SLV_CLKEN (1 << 19) > +#define I2S_MST_CLKEN (1 << 20) > +#define GPT1_CLKEN (1 << 21) > +#define GPT2_CLKEN (1 << 22) > +#define GPIO1_CLKEN (1 << 23) > +#define GPIO2_CLKEN (1 << 24) > +#define DMA1_CLKEN (1 << 25) > +#define DMA2_CLKEN (1 << 26) > +#define CLCD_CLKEN (1 << 27) > +#define JPEG_CLKEN (1 << 28) > +#define C3_CLKEN (1 << 29) > +#define ADC_CLKEN (1 << 30) > +#define RTC_CLKEN (1 << 31) > + > +#define DDR_CTRL_CLKEN (1 << 0) /* > perip2 */ > +#define DDR_CORE_CLKEN (1 << 1) > +#define CPU_DBG_CLKEN (1 << 2) > +#define KBD_CLKEN (1 << 3) > +#define GPT3_CLKEN (1 << 4) > +#define GPT4_CLKEN (1 << 5) > +#define ACP_CLKEN (1 << 6) > +#define I2S_REFOUT_CLKEN (1 << 7) > +#define THSENS_CLKEN (1 << 8) > + > +/* fsmc_cfg definitions */ > +#define DEV_SEL_NOR (0 << 0) > +#define DEV_SEL_NAND (1 << 0) > +#define DEV_SEL_SRAM (2 << 0) > +#define DEV_SEL_MSK (3 << 0) > +#define NAND_BANK_0 (0 << 2) > +#define NAND_BANK_1 (1 << 2) > +#define NAND_BANK_2 (2 << 2) > +#define NAND_BANK_3 (3 << 2) > +#define DEV_WIDTH_8 (0 << 4) > +#define DEV_WIDTH_16 (1 << 4) > + > +/* usbphy_gen_cfg definitions */ > +#define COMMON_PWDN (1 << 0) > +#define USBPHY_POR (1 << 12) > +#define USBPHY_RST (1 << 13) > +#define UTMI_XFER_RST0 (1 << 14) > +#define UTMI_XFER_RST1 (1 << 15) > +#define UTMI_XFER_RST2 (1 << 16) > +#define USB_PLL_LOCK (1 << 27) > + > +/* synth registers definitions */ > +#define SYNT_CLK_ENB (1 << 31) > +#define SYNT_FIN_FULL (1 << 30) > +#define SYNT_X_1 (1 << 16) > +#define SYNT_Y_2 (2 << 0) > +#define SYNT_Y_5 (5 << 0) > + > +/* gmac_clk_cfg definitions */ > +#define PHY_IF_GMII (0 << 4) > +#define PHY_IF_RGMII (1 << 4) > +#define PHY_IF_RMII (4 << 4) > +#define GMII_SYNT_ENB (1 << 3) > +#define CLK_SEL_PAD (0 << 0) > +#define CLK_SEL_PLL2 (1 << 0) > +#define CLK_SEL_OSCI3 (2 << 0) > + > +#endif > diff --git a/arch/arm/include/asm/arch-spear13xx/sys_proto.h > b/arch/arm/include/asm/arch-spear13xx/sys_proto.h > new file mode 100644 > index 0000000..e6cc3a9 > --- /dev/null > +++ b/arch/arm/include/asm/arch-spear13xx/sys_proto.h > @@ -0,0 +1,32 @@ > +/* > + * (C) Copyright 2009 > + * Vipin Kumar, STMicroelectronics, <vipin.ku...@st.com> > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#ifndef _SYS_PROTO_H_ > +#define _SYS_PROTO_H_ > + > +u32 get_device_type(void); This is needed for omap3. Remove Tom > +void invalidate_dcache(u32); > +void l2_cache_disable(void); > +void l2_cache_enable(void); > + > +#endif _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot