On 3/14/19 11:51 AM, Patrice Chotard wrote: > All TX fifo size can be different, add tx_fifo_sz_array[] > into dwc2_plat_otg_data to be able to set them. > > tx_fifo_sz_array[] is 17 Bytes long and can contains max 16 > tx fifo size (synopsys IP supports max 16 IN endpoints). > First entry of tx_fifo_sz_array[] is the number of valid > fifo size the array contains. > > In case of tx_fifo_sz_array[] doesn't contains the same > number of element than max hardware endpoint, display > a warning message. > > Compatibility with board which doesn't use tx_fifo_sz_array[] > (Rockchip rk322x/rk3128/rv1108/rk3288/rk3036) is kept. > > Signed-off-by: Patrice Chotard <patrice.chot...@st.com> > --- > > drivers/usb/gadget/dwc2_udc_otg.c | 13 +++++++++++-- > include/usb/dwc2_udc.h | 6 ++++++ > 2 files changed, 17 insertions(+), 2 deletions(-) > > diff --git a/drivers/usb/gadget/dwc2_udc_otg.c > b/drivers/usb/gadget/dwc2_udc_otg.c > index 3f0a012949ec..b9e4f0b5193d 100644 > --- a/drivers/usb/gadget/dwc2_udc_otg.c > +++ b/drivers/usb/gadget/dwc2_udc_otg.c > @@ -401,6 +401,7 @@ static void reconfig_usbd(struct dwc2_udc *dev) > uint32_t dflt_gusbcfg; > uint32_t rx_fifo_sz, tx_fifo_sz, np_tx_fifo_sz; > u32 max_hw_ep; > + int pdata_hw_ep; > > debug("Reseting OTG controller\n"); > > @@ -486,11 +487,19 @@ static void reconfig_usbd(struct dwc2_udc *dev) > /* retrieve the number of TX fifo */ > max_hw_ep = (readl(®->ghwcfg4) & GHWCFG4_NUM_IN_EPS_MASK) >> > GHWCFG4_NUM_IN_EPS_SHIFT; > + pdata_hw_ep = dev->pdata->tx_fifo_sz_array[DWC2_SIZE_NB_OFFS]; > > - for (i = 1; i < max_hw_ep; i++) > + if (pdata_hw_ep && max_hw_ep != pdata_hw_ep) > + pr_warn("Got %d hw endpoint and %d tx-fifo-size in array !!\n", > + max_hw_ep, pdata_hw_ep);
dev_warn() ? Also reword the warning a bit, it's not clear to me what it warns about. > + > + for (i = 1; i < max_hw_ep; i++) { > + if (pdata_hw_ep) > + tx_fifo_sz = dev->pdata->tx_fifo_sz_array[i + > + DWC2_SIZE_OFFS]; > writel((rx_fifo_sz + np_tx_fifo_sz + tx_fifo_sz*(i-1)) | > tx_fifo_sz << 16, ®->dieptxf[i-1]); > - > + } > /* Flush the RX FIFO */ > writel(RX_FIFO_FLUSH, ®->grstctl); > while (readl(®->grstctl) & RX_FIFO_FLUSH) > diff --git a/include/usb/dwc2_udc.h b/include/usb/dwc2_udc.h > index 4068de045dc2..871aecdca322 100644 > --- a/include/usb/dwc2_udc.h > +++ b/include/usb/dwc2_udc.h > @@ -10,6 +10,10 @@ > > #define PHY0_SLEEP (1 << 5) > > +#define DWC2_MAX_HW_ENDPOINTS 16 > +#define DWC2_SIZE_NB_OFFS 0 > +#define DWC2_SIZE_OFFS 1 > + > struct dwc2_plat_otg_data { > void *priv; > int phy_of_node; > @@ -22,6 +26,8 @@ struct dwc2_plat_otg_data { > unsigned int rx_fifo_sz; > unsigned int np_tx_fifo_sz; > unsigned int tx_fifo_sz; > + /* [0] number of element, [1..17] tx_fifo_sz (max 16 endpoints)*/ Just create a separate entry for the array size, please. Could be unsigned char too. > + unsigned int tx_fifo_sz_array[DWC2_MAX_HW_ENDPOINTS + 1]; > }; > > int dwc2_udc_probe(struct dwc2_plat_otg_data *pdata); > -- Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot