On 3/30/19 10:18 PM, Simon Glass wrote: > Hi Marek, > > On Sat, 23 Mar 2019 at 11:55, Marek Vasut <ma...@denx.de> wrote: >> >> The driver currently calculates the end address of cache flush operation >> for the DMA descriptors by adding cacheline size to the start address of >> the last DMA descriptor. This is not safe, as the cacheline size may be, >> in some unlikely cases, smaller than the DMA descriptor size. Replace the >> addition with roundup() applied on the end address of the last DMA >> descriptor to round it up to the nearest cacheline size multiple. >> >> Signed-off-by: Marek Vasut <ma...@denx.de> >> Cc: Jaehoon Chung <jh80.ch...@samsung.com> >> Cc: Simon Glass <s...@chromium.org> >> --- >> drivers/mmc/dw_mmc.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c >> index 72570235cb..bec30b1479 100644 >> --- a/drivers/mmc/dw_mmc.c >> +++ b/drivers/mmc/dw_mmc.c >> @@ -74,15 +74,15 @@ static void dwmci_prepare_data(struct dwmci_host *host, >> dwmci_set_idma_desc(cur_idmac, flags, cnt, >> (ulong)bounce_buffer + (i * PAGE_SIZE)); >> >> + cur_idmac++; > > What is this change for? I don't see it mentioned above.
AFAIR you need to increment the pointer to cur_idmac before breaking out of the loop, otherwise data_end might point a bit before the actual end of the buffer. >> if (blk_cnt <= 8) >> break; >> blk_cnt -= 8; >> - cur_idmac++; >> i++; >> } while(1); >> >> data_end = (ulong)cur_idmac; >> - flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN); >> + flush_dcache_range(data_start, roundup(data_end, ARCH_DMA_MINALIGN)); >> >> ctrl = dwmci_readl(host, DWMCI_CTRL); >> ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN; >> -- >> 2.20.1 >> > > Regards, > Simon > -- Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
