Hi Prabhakar, > -----Original Message----- > From: Prabhakar Kushwaha > Sent: 2019年4月7日 17:58 > To: Andy Tang <andy.t...@nxp.com> > Cc: albert.u.b...@aribaud.net; Sudhanshu Gupta <sudhanshu.gu...@nxp.com>; > Harninder Rai <harninder....@nxp.com>; Rajesh Bhagat > <rajesh.bha...@nxp.com>; Bhaskar Upadhaya <bhaskar.upadh...@nxp.com>; > u-boot@lists.denx.de; Andy Tang <andy.t...@nxp.com> > Subject: RE: [PATCH 1/3 v2] armv8: ls1028a: Add NXP LS1028A SoC support > > > > -----Original Message----- > > From: Yuantian Tang <andy.t...@nxp.com> > > Sent: Wednesday, April 3, 2019 12:48 PM > > To: Prabhakar Kushwaha <prabhakar.kushw...@nxp.com> > > Cc: albert.u.b...@aribaud.net; Sudhanshu Gupta > > <sudhanshu.gu...@nxp.com>; Harninder Rai <harninder....@nxp.com>; > > Rajesh Bhagat <rajesh.bha...@nxp.com>; Bhaskar Upadhaya > > <bhaskar.upadh...@nxp.com>; u-boot@lists.denx.de; Andy Tang > > <andy.t...@nxp.com> > > Subject: [PATCH 1/3 v2] armv8: ls1028a: Add NXP LS1028A SoC support > > > > LS1028A processor integrates two 64-bit Arm Cortex-A72 cores with a > > GPU and LCD controller, as well as TSN-enabled Ethernet ports and a > > TSN-enabled switch with four external ports. > > The high performance Cortex-A72 cores, performing above 16,000 > > CoreMarks, combined with 2.5 Gbit Ethernet, PCI express Gen 3.0, SATA > > 3.0, USB 3.0 and Octal/Quad SPI interfaces provide capabilities for a > > number of industrial and embedded applications. The device provides > > excellent integration with the new Time-Sensitive Networking standards > > and enables a number of TSN applications > > > > Features Summary > > * Two 32/64-bit Arm v8 Cortex-A72 CPUs > > * Cache coherent interconnect fabric (CCI-400) > > * 32-bit DDR3L/DDR4 SDRAM memory controller with ECC support > > * LCD controller and DisplayPort/eDP interface > > * Graphics processing unit > > * TSN-capable Ethernet Switch with four external ports > > * Ethernet Controller (ENETC) with TSN functionality > > * Four SerDes lanes with two PLLs for high-speed peripheral interfaces > > * Additional peripheral interfaces > > * Two high-speed USB 3.0 controllers > > * Two eSDHC controllers > > * Two controller area network (FlexCAN) modules > > * supporting flexible datarate (FD) > > * Three serial peripheral interface (SPI) controllers > > * Flexible SPI interface (FlexSPI) controller > > * Eight I2C controllers > > * Six LPUARTs > > * 16550-compliant DUART > > * General Purpose IO (GPIO) > > * Eight FlexTimers/PWM controllers > > * Six asynchronous audio interface (SAI) > > * Support for hardware virtualization and partitioning enforcement > > * QorIQ platform's trust architecture 3.0 > > * Queue direct memory access controller (qDMA) > > * Enhanced direct memory access controller (eDMA) > > * Global programmable interrupt controller (GIC) > > * Arm generic timer > > * Thermal Monitor Unit (TMU) > > > > It looks to be marketing description > This patch is not supporting all above features. So update description with > whatever supported by this patch. It listed all the features SOC supports, not the features this PATCH supports. We should give a full feature list when a new soc was added.
> > > > Signed-off-by: Sudhanshu Gupta <sudhanshu.gu...@nxp.com> > > Signed-off-by: Rai Harninder <harninder....@nxp.com> > > Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com> > > Signed-off-by: Bhaskar Upadhaya <bhaskar.upadh...@nxp.com> > > Signed-off-by: Tang Yuantian <andy.t...@nxp.com> > > --- > > v2: > > - fix many issues > > arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 39 ++- > > arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 + > > arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 + > > arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 51 ++++ > > arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c | 88 +++++++ > > arch/arm/dts/fsl-ls1028a.dtsi | 280 > +++++++++++++++++++++ > > arch/arm/include/asm/arch-fsl-layerscape/config.h | 61 +++++ > > .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 16 ++ > > .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 9 + > > arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 + > > .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 2 +- > > 11 files changed, 552 insertions(+), 2 deletions(-) create mode 100644 > > arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c > > create mode 100644 arch/arm/dts/fsl-ls1028a.dtsi > > > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > > b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > > index f48481f..8ecd095 100644 > > --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > > +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > > @@ -20,6 +20,40 @@ config ARCH_LS1012A > > select SYS_I2C_MXC_I2C2 > > imply PANIC_HANG > > > > +config ARCH_LS1028A > > + bool > > + select ARMV8_SET_SMPEN > > + select FSL_LSCH3 > > + select NXP_LSCH3_2 > > + select SYS_FSL_HAS_CCI400 > > + select SYS_FSL_SRDS_1 > > + select SYS_HAS_SERDES > > + select SYS_FSL_DDR > > + select SYS_FSL_DDR_LE > > + select SYS_FSL_DDR_VER_50 > > + select SYS_FSL_HAS_DDR3 > > + select SYS_FSL_HAS_DDR4 > > + select SYS_FSL_HAS_SEC > > + select SYS_FSL_SEC_COMPAT_5 > > + select SYS_FSL_SEC_LE > > + select FSL_TZASC_1 > > + select ARCH_EARLY_INIT_R > > + select BOARD_EARLY_INIT_F > > + select SYS_I2C_MXC > > + select SYS_I2C_MXC_I2C1 > > + select SYS_I2C_MXC_I2C2 > > + select SYS_I2C_MXC_I2C3 > > + select SYS_I2C_MXC_I2C4 > > + select SYS_I2C_MXC_I2C5 > > + select SYS_I2C_MXC_I2C6 > > + select SYS_I2C_MXC_I2C7 > > + select SYS_I2C_MXC_I2C8 > > + select SYS_FSL_ERRATUM_A009007 > > + select SYS_FSL_ERRATUM_A008514 if !TFABOOT > > + select SYS_FSL_ERRATUM_A009663 if !TFABOOT > > + select SYS_FSL_ERRATUM_A009942 if !TFABOOT > > + imply PANIC_HANG > > + > > config ARCH_LS1043A > > bool > > select ARMV8_SET_SMPEN > > @@ -244,6 +278,7 @@ config FSL_PCIE_COMPAT > > string "PCIe compatible of Kernel DT" > > depends on PCIE_LAYERSCAPE > > default "fsl,ls1012a-pcie" if ARCH_LS1012A > > + default "fsl,ls1028a-pcie" if ARCH_LS1028A > > default "fsl,ls1043a-pcie" if ARCH_LS1043A > > default "fsl,ls1046a-pcie" if ARCH_LS1046A > > default "fsl,ls2080a-pcie" if ARCH_LS2080A @@ -343,6 +378,7 @@ > > config SYS_FSL_ERRATUM_A010539 > > > > config MAX_CPUS > > int "Maximum number of CPUs permitted for Layerscape" > > + default 2 if ARCH_LS1028A > > default 4 if ARCH_LS1043A > > default 4 if ARCH_LS1046A > > default 16 if ARCH_LS2080A > > @@ -377,7 +413,7 @@ config QSPI_AHB_INIT config SYS_CCI400_OFFSET > > hex "Offset for CCI400 base" > > depends on SYS_FSL_HAS_CCI400 > > - default 0x3090000 if ARCH_LS1088A > > + default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A > > default 0x180000 if FSL_LSCH2 > > help > > Offset for CCI400 base > > @@ -446,6 +482,7 @@ config CLUSTER_CLK_FREQ > > > > config SYS_FSL_PCLK_DIV > > int "Platform clock divider" > > + default 1 if ARCH_LS1028A > > default 1 if ARCH_LS1043A > > default 1 if ARCH_LS1046A > > default 1 if ARCH_LS1088A > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile > > b/arch/arm/cpu/armv8/fsl-layerscape/Makefile > > index e9bc987..a8d3cf9 100644 > > --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile > > +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile > > @@ -48,3 +48,7 @@ endif > > ifneq ($(CONFIG_ARCH_LS1088A),) > > obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o endif > > + > > +ifneq ($(CONFIG_ARCH_LS1028A),) > > +obj-$(CONFIG_SYS_HAS_SERDES) += ls1028a_serdes.o endif > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c > > b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c > > index 978d46b..657d13c 100644 > > --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c > > +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c > > @@ -58,6 +58,7 @@ static struct cpu_type cpu_type_list[] = { > > CPU_TYPE_ENTRY(LS1026A, LS1026A, 2), > > CPU_TYPE_ENTRY(LS2040A, LS2040A, 4), > > CPU_TYPE_ENTRY(LS1012A, LS1012A, 1), > > + CPU_TYPE_ENTRY(LS1028A, LS1028A, 2), > > CPU_TYPE_ENTRY(LS1088A, LS1088A, 8), > > CPU_TYPE_ENTRY(LS1084A, LS1084A, 8), > > CPU_TYPE_ENTRY(LS1048A, LS1048A, 4), > > @@ -246,11 +247,13 @@ static struct mm_region final_map[] = { > > PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > > PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN > > }, > > +#ifndef CONFIG_ARCH_LS1028A > > Please avoid using SoC specific #ifndef. Use #ifdef > CONFIG_SYS_PCIE3_PHYS_ADDR > And change code accordingly. A: Okay > > > { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, > > CONFIG_SYS_PCIE3_PHYS_SIZE, > > PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > > PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN > > }, > > +#endif > > #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) > > { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, > > CONFIG_SYS_PCIE4_PHYS_SIZE, > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc > > b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc > > index a0e2621..ad55573 100644 > > --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc > > +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc > > @@ -8,6 +8,7 @@ SoC overview > > 6. LS2088A > > 7. LS2081A > > 8. LX2160A > > + 9. LS1028A > > > > LS1043A > > --------- > > @@ -328,3 +329,53 @@ LX2160A SoC has 2 more similar SoC personalities > > > > 2)LX2080A, few difference w.r.t. LX2160A: > > a) Eight 64-bit ARM v8 Cortex-A72 CPUs > > + > > + > > +LS1028A > > +-------- > > +The QorIQ LS1028A processor integrates two 64-bit Arm Cortex-A72 cores > > +with a GPU and LCD controller, as well as two TSN-enabled Ethernet > > +controllers and a TSNenabled 4-port switch. > > + > > +The high performance Cortex-A72 cores, performing above 16,000 > > +CoreMarks, combined with 2.5 Gbit Ethernet, PCI express Gen 3.0, SATA > > +3.0, USB 3.0 and Octal/Quad SPI interfaces provide capabilities for a > > +number of industrial and embedded applications. The device provides > > +excellent integration with the new Time-Sensitive Networking standard, > > +and enables a number of TSN applications. > > + > > +The LS1028A SoC includes the following function and features: > > + - Two 64-bit ARM v8 A72 CPUs > > + - Cache Coherent interconnect (CCI-400) > > + - One 32-bit DDR3L/DDR4 SDRAM memory controller with ECC > > + - eDP/Displayport interface > > + - Graphics processing unit > > + - One Configurable x4 SerDes > > + - Ethernet interfaces > > + - Non-switched: One Ethernet MAC supporting 2.5G, 1G, 100M, 10M, one > > + ethernet MAC supporting 1G, 100M, 10M. > > + - Switched: TSN IP to support four 2.5/1G interfaces. > > + - None of the MACs support MACSEC > > + - Support for RGMII, SGMII (and 1000Base-KX), SGMII 2.5x, QSGMII > > + - Support for 10G-SXGMII and 10G-QXGMII. > > + - Energy efficient Ethernet support (802.3az) > > + - IEEE 1588 support > > + - High-speed peripheral interfaces > > + - Two PCIe 3.0 controllers, one supporting x4 operation > > + - One serial ATA (SATA 3.0) controller > > + - Additional peripheral interfaces > > + - Two high-speed USB 2.0/3.0 controllers with integrated PHY each > > + supporting host or device modes > > + - Two Enhanced secure digital host controllers (SD/SDIO/eMMC) > > + - Two Serial peripheral interface (SPI) controllers > > + - Eight I2C controllers > > + - Two UART controllers > > + - Additional six Industrual UARTs (LPUART). > > + - One FlexSPI controller > > + - General Purpose IO (GPIO) > > + - Two CAN-FD interfaces > > + - Eight Flextimers with PWM I/O > > + - Support for hardware virtualization and partitioning enforcement > > + - Layerscape Trust Architecture > > + - Service Processor (SP) provides pre-boot initialization and secure-boot > > + capabilities > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c > > b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c > > new file mode 100644 > > index 0000000..f5f264c > > --- /dev/null > > +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c > > @@ -0,0 +1,88 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright 2019 NXP > > + */ > > + > > +#include <common.h> > > +#include <asm/arch/fsl_serdes.h> > > + > > +struct serdes_config { > > + u32 protocol; > > + u8 lanes[SRDS_MAX_LANES]; > > + u8 rcw_lanes[SRDS_MAX_LANES]; > > +}; > > + > > +static struct serdes_config serdes1_cfg_tbl[] = { > > + /* SerDes 1 */ > > + {0xE031, {SXGMII1, QXGMII2, NONE, SATA1} }, > > + {0xB991, {SXGMII1, SGMII1, SGMII2, PCIE1} }, > > + {0xBB31, {SXGMII1, QXGMII2, PCIE1, PCIE1} }, > > + {0xCC31, {SXGMII1, QXGMII2, PCIE2, PCIE2} }, > > + {0xBB51, {SXGMII1, QSGMII_B, PCIE2, PCIE1} }, > > + {0xCC51, {SXGMII1, QSGMII_B, PCIE2, PCIE2} }, > > + {0xCC3B, {PCIE1, QXGMII2, PCIE2, PCIE2} }, > > + {0xCC5B, {PCIE1, QSGMII_B, PCIE2, PCIE2} }, > > + {0xBB38, {SGMII_T1, QXGMII2, PCIE2, PCIE1} }, > > + {0xCC38, {SGMII_T1, QXGMII2, PCIE2, PCIE2} }, > > + {0xBB58, {SGMII_T1, QSGMII_B, PCIE2, PCIE1} }, > > + {0xEB99, {SGMII1, SGMII1, PCIE2, SATA1} }, > > + {0xCC99, {SGMII1, SGMII1, PCIE2, PCIE2} }, > > + {0xBB99, {SGMII1, SGMII1, PCIE2, PCIE1} }, > > + {0xCC58, {SGMII_T1, QSGMII_B, PCIE2, PCIE2} }, > > + {0xCC8B, {PCIE1, SGMII_T1, PCIE2, PCIE2} }, > > + {0x9999, {SGMII1, SGMII2, SGMII3, SGMII4} }, > > + {0xEB58, {SGMII_T1, QSGMII_B, PCIE2, SATA1} }, > > + {0xEB8B, {PCIE1, SGMII_T1, PCIE2, SATA1} }, > > + {0xE8CC, {PCIE1, PCIE1, SGMII_T1, SATA1} }, > > + {0xEBCC, {PCIE1, PCIE1, PCIE2, SATA1} }, > > + {0xCCCC, {PCIE1, PCIE1, PCIE2, PCIE2} }, > > + {0xDDDD, {PCIE1, PCIE1, PCIE1, PCIE1} }, > > + {} > > +}; > > + > > +static struct serdes_config *serdes_cfg_tbl[] = { > > + serdes1_cfg_tbl, > > +}; > > + > > +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) { > > + struct serdes_config *ptr; > > + > > + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) > > + return 0; > > + > > + ptr = serdes_cfg_tbl[serdes]; > > + while (ptr->protocol) { > > + if (ptr->protocol == cfg) > > + return ptr->lanes[lane]; > > + ptr++; > > + } > > + > > + return 0; > > +} > > + > > +int is_serdes_prtcl_valid(int serdes, u32 prtcl) { > > + int i; > > + struct serdes_config *ptr; > > + > > + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) > > + return 0; > > + > > + ptr = serdes_cfg_tbl[serdes]; > > + while (ptr->protocol) { > > + if (ptr->protocol == prtcl) > > + break; > > + ptr++; > > + } > > + > > + if (!ptr->protocol) > > + return 0; > > + > > + for (i = 0; i < SRDS_MAX_LANES; i++) { > > + if (ptr->lanes[i] != NONE) > > + return 1; > > + } > > + > > + return 0; > > +} > > diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi > new > > file mode 100644 index 0000000..a38c8ce > > --- /dev/null > > +++ b/arch/arm/dts/fsl-ls1028a.dtsi > > @@ -0,0 +1,280 @@ > > +// SPDX-License-Identifier: GPL-2.0+ OR X11 > > +/* > > + * NXP ls1028a SOC common device tree source > > + * > > + * Copyright 2019 NXP > > + * > > + */ > > + > > +/ { > > + compatible = "fsl,ls1028a"; > > + interrupt-parent = <&gic>; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + sysclk: sysclk { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <100000000>; > > + clock-output-names = "sysclk"; > > + }; > > + > > + clockgen: clocking@1300000 { > > + compatible = "fsl,ls1028a-clockgen"; > > + reg = <0x0 0x1300000 0x0 0xa0000>; > > + #clock-cells = <2>; > > + clocks = <&sysclk>; > > + }; > > + > > + memory@01080000 { > > + device_type = "memory"; > > + reg = <0x00000000 0x01080000 0 0x80000000>; > > + /* DRAM space - 1, size : 2 GB DRAM */ > > + }; > > + > > + gic: interrupt-controller@6000000 { > > + compatible = "arm,gic-v3"; > > + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ > > + <0x0 0x06040000 0 0x40000>; > > + #interrupt-cells = <3>; > > + interrupt-controller; > > + interrupts = <1 9 0x4>; > > + }; > > + > > + timer { > > + compatible = "arm,armv8-timer"; > > + interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ > > + <1 14 0x8>, /* Physical Non-Secure PPI, active-low > > */ > > + <1 11 0x8>, /* Virtual PPI, active-low */ > > + <1 10 0x8>; /* Hypervisor PPI, active-low */ > > + }; > > + > > + fspi: flexspi@20C0000 { > > + compatible = "nxp,dn-fspi"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <0x0 0x20C0000 0x0 0x10000>, > > + <0x0 0x20000000 0x0 0x10000000>; /*64MB flash*/ > > + reg-names = "FSPI", "FSPI-memory"; > > + num-cs = <1>; > > + status = "disabled"; > > + }; > > + > > + serial0: serial@21c0500 { > > + device_type = "serial"; > > + compatible = "fsl,ns16550", "ns16550a"; > > + reg = <0x0 0x21c0500 0x0 0x100>; > > + interrupts = <0 32 0x1>; /* edge triggered */ > > + status = "disabled"; > > + }; > > + > > + serial1: serial@21c0600 { > > + device_type = "serial"; > > + compatible = "fsl,ns16550", "ns16550a"; > > + reg = <0x0 0x21c0600 0x0 0x100>; > > + interrupts = <0 32 0x1>; /* edge triggered */ > > + status = "disabled"; > > + }; > > + > > + pcie@3400000 { /* rcie_enetc */ > > This patch does not have support of enetc. So avoid references of entc A: many IPs this patch doesn't support, like USB, sata, clock..., they all should be removed? > > > + compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie"; > > + reg = <0x00 0x03400000 0x0 0x80000 > > + 0x00 0x03480000 0x0 0x40000 /* lut registers */ > > + 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */ > > + 0x80 0x00000000 0x0 0x20000>; /* configuration space */ > > + reg-names = "dbi", "lut", "ctrl", "config"; > > + #address-cells = <3>; > > + #size-cells = <2>; > > + device_type = "pci"; > > + num-lanes = <4>; > > + bus-range = <0x0 0xff>; > > + ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 > > 0x00010000 /* downstream I/O */ > > + 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 > > 0x40000000>; /* non-prefetchable memory */ > > + }; > > + > > + pcie@3500000 { > > + compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie"; > > + reg = <0x00 0x03500000 0x0 0x80000 > > + 0x00 0x03580000 0x0 0x40000 /* lut registers */ > > + 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */ > > + 0x88 0x00000000 0x0 0x20000>; /* configuration space */ > > + reg-names = "dbi", "lut", "ctrl", "config"; > > + #address-cells = <3>; > > + #size-cells = <2>; > > + device_type = "pci"; > > + num-lanes = <4>; > > + bus-range = <0x0 0xff>; > > + ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 > > 0x00010000 /* downstream I/O */ > > + 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 > > 0x40000000>; /* non-prefetchable memory */ > > + }; > > + > > + i2c0: i2c@2000000 { > > + compatible = "fsl,vf610-i2c"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <0x0 0x2000000 0x0 0x10000>; > > + interrupts = <0 34 0x4>; > > + clock-names = "i2c"; > > + clocks = <&clockgen 4 0>; > > + status = "disabled"; > > + }; > > + > > + i2c1: i2c@2010000 { > > + compatible = "fsl,vf610-i2c"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <0x0 0x2010000 0x0 0x10000>; > > + interrupts = <0 34 0x4>; > > + clock-names = "i2c"; > > + clocks = <&clockgen 4 0>; > > + status = "disabled"; > > + }; > > + > > + i2c2: i2c@2020000 { > > + compatible = "fsl,vf610-i2c"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <0x0 0x2020000 0x0 0x10000>; > > + interrupts = <0 35 0x4>; > > + clock-names = "i2c"; > > + clocks = <&clockgen 4 0>; > > + status = "disabled"; > > + }; > > + > > + i2c3: i2c@2030000 { > > + compatible = "fsl,vf610-i2c"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <0x0 0x2030000 0x0 0x10000>; > > + interrupts = <0 35 0x4>; > > + clock-names = "i2c"; > > + clocks = <&clockgen 4 0>; > > + status = "disabled"; > > + }; > > + > > + i2c4: i2c@2040000 { > > + compatible = "fsl,vf610-i2c"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <0x0 0x2040000 0x0 0x10000>; > > + interrupts = <0 74 0x4>; > > + clock-names = "i2c"; > > + clocks = <&clockgen 4 0>; > > + status = "disabled"; > > + }; > > + > > + i2c5: i2c@2050000 { > > + compatible = "fsl,vf610-i2c"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <0x0 0x2050000 0x0 0x10000>; > > + interrupts = <0 74 0x4>; > > + clock-names = "i2c"; > > + clocks = <&clockgen 4 0>; > > + status = "disabled"; > > + }; > > + > > + i2c6: i2c@2060000 { > > + compatible = "fsl,vf610-i2c"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <0x0 0x2060000 0x0 0x10000>; > > + interrupts = <0 75 0x4>; > > + clock-names = "i2c"; > > + clocks = <&clockgen 4 0>; > > + status = "disabled"; > > + }; > > + > > + i2c7: i2c@2070000 { > > + compatible = "fsl,vf610-i2c"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <0x0 0x2070000 0x0 0x10000>; > > + interrupts = <0 75 0x4>; > > + clock-names = "i2c"; > > + clocks = <&clockgen 4 0>; > > + status = "disabled"; > > + }; > > + > > + usb1: usb3@3100000 { > > + compatible = "fsl,layerscape-dwc3"; > > + reg = <0x0 0x3100000 0x0 0x10000>; > > + interrupts = <0 80 0x4>; > > + dr_mode = "host"; > > + status = "disabled"; > > + }; > > + > > + usb2: usb3@3110000 { > > + compatible = "fsl,layerscape-dwc3"; > > + reg = <0x0 0x3110000 0x0 0x10000>; > > + interrupts = <0 81 0x4>; > > + dr_mode = "host"; > > + status = "disabled"; > > + }; > > + > > + dspi0: dspi@2100000 { > > + compatible = "fsl,vf610-dspi"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <0x0 0x2100000 0x0 0x10000>; > > + interrupts = <0 26 0x4>; > > + clock-names = "dspi"; > > + clocks = <&clockgen 4 0>; > > + num-cs = <5>; > > + litte-endian; > > + status = "disabled"; > > + }; > > + > > + dspi1: dspi@2110000 { > > + compatible = "fsl,vf610-dspi"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <0x0 0x2110000 0x0 0x10000>; > > + interrupts = <0 26 0x4>; > > + clock-names = "dspi"; > > + clocks = <&clockgen 4 0>; > > + num-cs = <5>; > > + little-endian; > > + status = "disabled"; > > + }; > > + > > + dspi2: dspi@2120000 { > > + compatible = "fsl,vf610-dspi"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <0x0 0x2120000 0x0 0x10000>; > > + interrupts = <0 26 0x4>; > > + clock-names = "dspi"; > > + clocks = <&clockgen 4 0>; > > + num-cs = <5>; > > + little-endian; > > + status = "disabled"; > > + }; > > + > > + esdhc0: esdhc@2140000 { > > + compatible = "fsl,esdhc"; > > + reg = <0x0 0x2140000 0x0 0x10000>; > > + interrupts = <0 28 0x4>; > > + big-endian; > > + bus-width = <4>; > > + status = "disabled"; > > + }; > > + > > + esdhc1: esdhc@2150000 { > > + compatible = "fsl,esdhc"; > > + reg = <0x0 0x2150000 0x0 0x10000>; > > + interrupts = <0 63 0x4>; > > + big-endian; > > + non-removable; > > + bus-width = <4>; > > + status = "disabled"; > > + }; > > + > > + sata: sata@3200000 { > > + compatible = "fsl,ls1028a-ahci"; > > + reg = <0x0 0x3200000 0x0 0x10000>; > > + interrupts = <0 133 4>; > > + clocks = <&clockgen 4 1>; > > + status = "disabled"; > > + }; > > +}; > > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h > > b/arch/arm/include/asm/arch-fsl-layerscape/config.h > > index 903d509..eb21c09 100644 > > --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h > > +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h > > @@ -229,6 +229,67 @@ > > > > #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 > > > > +#elif defined(CONFIG_ARCH_LS1028A) > > +#define CONFIG_SYS_FSL_NUM_CC_PLLS 3 > > +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } > > +#define CONFIG_GICV3 > > +#define CONFIG_FSL_TZPC_BP147 > > +#define CONFIG_FSL_TZASC_400 > > + > > +/* TZ Protection Controller Definitions */ > > +#define TZPC_BASE 0x02200000 > > +#define TZPCR0SIZE_BASE (TZPC_BASE) > > +#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) > > +#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) > > +#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) > > +#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) > > +#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) > > +#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) > > +#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) > > +#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) > > +#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) > > + > > +#define SRDS_MAX_LANES 4 > > + > > +#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial > > RAM */ > > +#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M */ > > +#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size > 256K > > */ > > + > > +/* Generic Interrupt Controller Definitions */ > > +#define GICD_BASE 0x06000000 > > +#define GICR_BASE 0x06040000 > > + > > +/* SMMU Definitions */ > > +#define SMMU_BASE 0x05000000 /* GR0 Base */ > > + > > +/* DDR */ > > +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) > > +#define CONFIG_MAX_MEM_MAPPED > > CONFIG_SYS_DDR_BLOCK1_SIZE > > + > > +#define CONFIG_SYS_FSL_CCSR_GUR_LE > > +#define CONFIG_SYS_FSL_CCSR_SCFG_LE > > +#define CONFIG_SYS_FSL_ESDHC_LE > > +#define CONFIG_SYS_FSL_PEX_LUT_LE > > + > > +#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN > > + > > +/* SFP */ > > +#define CONFIG_SYS_FSL_SFP_VER_3_4 > > +#define CONFIG_SYS_FSL_SFP_LE > > +#define CONFIG_SYS_FSL_SRK_LE > > + > > +/* SEC */ > > +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 > > + > > +/* Security Monitor */ > > +#define CONFIG_SYS_FSL_SEC_MON_LE > > + > > +/* Secure Boot */ > > +#define CONFIG_ESBC_HDR_LS > > + > > +/* DCFG - GUR */ > > +#define CONFIG_SYS_FSL_CCSR_GUR_LE > > + > > #elif defined(CONFIG_FSL_LSCH2) > > #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial > > RAM */ > > #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ > > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h > > b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h > > index 68354ff..59b224b 100644 > > --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h > > +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h > > @@ -64,6 +64,22 @@ enum srds_prtcl { > > QSGMII_B, > > QSGMII_C, > > QSGMII_D, > > + SGMII_T1, > > + SGMII_T2, > > + SGMII_T3, > > + SGMII_T4, > > + SGMII_S1, > > + SGMII_S2, > > + SGMII_S3, > > + SGMII_S4, > > Can existing SGMII enum not be used? A: not sure, will remove it. BR, Andy > > > + SXGMII1, > > + SXGMII2, > > + SXGMII3, > > + SXGMII4, > > + QXGMII1, > > + QXGMII2, > > + QXGMII3, > > + QXGMII4, > > _25GE1, > > _25GE2, > > _25GE3, > > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h > > b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h > > index 9fab88a..dbf3215 100644 > > --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h > > +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h > > @@ -171,6 +171,9 @@ > > #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL > > #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL > > #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL > > +#elif CONFIG_ARCH_LS1028A > > +#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL > > +#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL > > #else > > #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL > > #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL > > @@ -375,6 +378,12 @@ struct ccsr_gur { > > #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT > > FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT > > #define FSL_CHASSIS3_SRDS1_REGSR 29 > > #define FSL_CHASSIS3_SRDS2_REGSR 30 > > +#elif defined(CONFIG_ARCH_LS1028A) > > +#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000 > > +#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16 > > +#define FSL_CHASSIS3_SRDS1_PRTCL_MASK > > FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK > > +#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT > > FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT > > +#define FSL_CHASSIS3_SRDS1_REGSR 29 > > #endif > > #define RCW_SB_EN_REG_INDEX 9 > > #define RCW_SB_EN_MASK 0x00000400 > > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h > > b/arch/arm/include/asm/arch-fsl-layerscape/soc.h > > index 7d95c4e..234440b 100644 > > --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h > > +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h > > @@ -83,6 +83,7 @@ enum boot_src get_boot_src(void); > > /* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER > */ > > #define SVR_LS1043A_P23 0x879202 > > #define SVR_LS1023A_P23 0x87920A > > +#define SVR_LS1028A 0x870B00 > > #define SVR_LS1046A 0x870700 > > #define SVR_LS1026A 0x870708 > > #define SVR_LS1048A 0x870320 > > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h > > b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h > > index e017d8b..c53cc57 100644 > > --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h > > +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h > > @@ -87,7 +87,7 @@ > > #define FSL_PEX_STREAM_ID_NUM (0x100) > > #endif > > > > -#if defined(CONFIG_ARCH_LS2080A) > > +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1028A) > > #define FSL_PEX_STREAM_ID_END 22 > > #elif defined(CONFIG_ARCH_LS1088A) > > #define FSL_PEX_STREAM_ID_END 18 > > -- > > 2.7.4 > > > --pk _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot