Hi, On 08/04/19 10:32 PM, Vignesh Raghavendra wrote: > This series adds a Kconfig to disable cache maintenance operations on > a coherent architectures. And disable cache flush/invalidate ops for > SPL/U-Boot code running on A53 core of AM654 SoC(which is IO coherent) > > Vignesh Raghavendra (2): > arch: armv8: Provide a way to disable cache maintenance ops > board: ti: am654: select SYS_DISABLE_DCACHE_OPS for arm64 build
Please ignore this patches. I found an issue with the patches. Will post a v2. > > arch/Kconfig | 9 +++++++++ > arch/arm/cpu/armv8/cache_v8.c | 18 ++++++++++++++++++ > board/ti/am65x/Kconfig | 1 + > 3 files changed, 28 insertions(+) > -- Regards Vignesh _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
