AM654 SoC is IO coherent wrt A53 cores, therefore enable
SYS_DISABLE_DCACHE_OPS to avoid cache operations in A53
SPL/U-Boot.
Signed-off-by: Vignesh Raghavendra <vigne...@ti.com>
---
board/ti/am65x/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/ti/am65x/Kconfig b/board/ti/am65x/Kconfig
index d4b36dbb42f3..98172c28f5d3 100644
--- a/board/ti/am65x/Kconfig
+++ b/board/ti/am65x/Kconfig
@@ -11,6 +11,7 @@ config TARGET_AM654_A53_EVM
bool "TI K3 based AM654 EVM running on A53"
select ARM64
select SOC_K3_AM6
+ select SYS_DISABLE_DCACHE_OPS
config TARGET_AM654_R5_EVM
bool "TI K3 based AM654 EVM running on R5"
--
2.21.0
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