From: Rick Chen <r...@andestech.com>
In current RISC-V SMP flow, AE350 will encounter the the write
failure problem since hart_lottery and available_harts_lock was
not in ram address but in flash address when booing from flash.
This patch can help to fix the failure problem when AE350 was
booting from flash by disable this two features.
Rick Chen (4):
riscv: hart_lottery and available harts feature can be seletable
riscv: configs: Support AE350 SMP boot from flash flow
riscv: prior_stage_fdt_address only be used when OF_PRIOR_STAGE is
enable
riscv: configs: AE350 will use OF_PRIOR_STAGE when boot from ram
arch/riscv/Kconfig | 21 ++++++++++++++++++++
arch/riscv/cpu/cpu.c | 4 ++++
arch/riscv/cpu/start.S | 11 ++++++++++-
arch/riscv/include/asm/global_data.h | 2 ++
arch/riscv/lib/asm-offsets.c | 2 ++
arch/riscv/lib/smp.c | 2 ++
configs/ae350_rv32_defconfig | 2 +-
configs/ae350_rv32_xip_defconfig | 37 +++++++++++++++++++++++++++++++++++
configs/ae350_rv64_defconfig | 2 +-
configs/ae350_rv64_xip_defconfig | 38 ++++++++++++++++++++++++++++++++++++
10 files changed, 118 insertions(+), 3 deletions(-)
create mode 100644 configs/ae350_rv32_xip_defconfig
create mode 100644 configs/ae350_rv64_xip_defconfig
--
2.7.4
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