> From: Ludwig Zenz <lz...@dh-electronics.de> > The four x16 DDR3 are wired in T-topology. From NXP AN4467: > 'Although not required, T-Topologies may also benefit from performing > Write Leveling as there are package delays on both the processor and DDR > devices that can be de-skewed by performing Write Leveling. Therefore, > Freescale recommends determining Write Leveling calibration parameters > for all boards, regardless of topology used.' > That is why write level calibration is also done. > Signed-off-by: Ludwig Zenz <lz...@dh-electronics.com>
Applied to u-boot-imx, master, thanks ! Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de ===================================================================== _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot