While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances
where these configuration items are conditional on SPL. This commit adds SPL
variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates
the configurations as required.
Acked-by: Alexey Brodkin <abrod...@synopsys.com>
Signed-off-by: Trevor Woerner <tre...@toganlabs.com>
---
Changes in v3: None
Changes in v2: None
arch/arc/Kconfig | 14 ++++++++++++++
arch/arc/lib/start.S | 4 ++--
arch/arm/Kconfig | 14 ++++++++++++++
arch/arm/cpu/arm11/cpu.c | 12 ++++++------
arch/arm/cpu/arm926ejs/cache.c | 12 ++++++------
arch/arm/cpu/arm926ejs/cpu.c | 2 +-
arch/arm/cpu/arm926ejs/start.S | 4 ++--
arch/arm/cpu/armv7/cache_v7.c | 8 ++++----
arch/arm/cpu/armv7/iproc-common/hwinit-common.c | 2 +-
arch/arm/cpu/armv7/kona-common/hwinit-common.c | 2 +-
arch/arm/cpu/armv7/ls102xa/cpu.c | 4 ++--
arch/arm/cpu/armv7/start.S | 4 ++--
arch/arm/cpu/armv7/vf610/generic.c | 2 +-
arch/arm/cpu/armv7m/cache.c | 8 ++++----
arch/arm/cpu/armv8/cache_v8.c | 12 ++++++------
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 4 ++--
arch/arm/cpu/armv8/s32v234/cpu.c | 2 +-
arch/arm/cpu/pxa/cache.c | 6 +++---
arch/arm/cpu/pxa/pxa2xx.c | 4 ++--
arch/arm/include/asm/global_data.h | 2 +-
arch/arm/lib/cache-cp15.c | 6 +++---
arch/arm/lib/cache.c | 2 +-
arch/arm/mach-exynos/soc.c | 2 +-
arch/arm/mach-imx/cache.c | 2 +-
arch/arm/mach-imx/imx8/cpu.c | 2 +-
arch/arm/mach-imx/mx5/soc.c | 2 +-
arch/arm/mach-keystone/init.c | 2 +-
arch/arm/mach-omap2/Makefile | 2 +-
arch/arm/mach-omap2/omap5/sec_entry_cpu1.S | 6 +++---
arch/arm/mach-omap2/sec-common.c | 4 ++--
arch/arm/mach-rmobile/cpu_info.c | 2 +-
arch/arm/mach-rockchip/rk3036-board.c | 2 +-
arch/arm/mach-rockchip/rk3128-board.c | 2 +-
arch/arm/mach-rockchip/rk3188-board.c | 2 +-
arch/arm/mach-rockchip/rk322x-board.c | 2 +-
arch/arm/mach-rockchip/rk3288-board.c | 2 +-
arch/arm/mach-rockchip/rv1108/rv1108.c | 2 +-
arch/arm/mach-s5pc1xx/cache.c | 2 +-
arch/arm/mach-socfpga/misc.c | 4 ++--
arch/arm/mach-sunxi/board.c | 2 +-
arch/arm/mach-tegra/board.c | 2 +-
arch/arm/mach-zynq/cpu.c | 2 +-
arch/nds32/Kconfig | 14 ++++++++++++++
arch/nds32/cpu/n1213/start.S | 8 ++++----
arch/nds32/lib/cache.c | 6 +++---
arch/riscv/Kconfig | 14 ++++++++++++++
arch/riscv/cpu/ax25/cache.c | 8 ++++----
arch/xtensa/Kconfig | 14 ++++++++++++++
arch/xtensa/cpu/start.S | 7 ++++---
board/st/stih410-b2260/board.c | 2 +-
cmd/bdinfo.c | 2 +-
common/board_f.c | 2 +-
common/lcd.c | 2 +-
configs/bitmain_antminer_s9_defconfig | 1 +
configs/imx8mq_evk_defconfig | 2 ++
configs/imx8qxp_mek_defconfig | 2 ++
configs/smartweb_defconfig | 2 ++
configs/syzygy_hub_defconfig | 1 +
configs/taurus_defconfig | 2 ++
configs/topic_miami_defconfig | 1 +
configs/topic_miamilite_defconfig | 1 +
configs/topic_miamiplus_defconfig | 1 +
configs/zynq_cse_nand_defconfig | 1 +
configs/zynq_cse_nor_defconfig | 1 +
configs/zynq_cse_qspi_defconfig | 1 +
drivers/dma/apbh_dma.c | 2 +-
drivers/mtd/nand/raw/mxs_nand.c | 2 +-
drivers/net/dwc_eth_qos.c | 2 +-
drivers/net/rtl8169.c | 2 +-
drivers/net/sh_eth.c | 3 ++-
drivers/video/video-uclass.c | 2 +-
include/configs/imx8mq_evk.h | 2 --
include/configs/imx8qxp_mek.h | 2 --
include/configs/mx7ulp_evk.h | 2 +-
include/configs/smartweb.h | 5 -----
include/configs/taurus.h | 4 ----
include/configs/zynq-common.h | 5 -----
77 files changed, 188 insertions(+), 118 deletions(-)
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 240d3bbedc..7d00666a3b 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -114,12 +114,26 @@ config SYS_ICACHE_OFF
help
Do not enable instruction cache in U-Boot.
+config SPL_SYS_ICACHE_OFF
+ bool "Do not enable icache in SPL"
+ depends on SPL
+ default n
+ help
+ Do not enable instruction cache in SPL.
+
config SYS_DCACHE_OFF
bool "Do not enable dcache"
default n
help
Do not enable data cache in U-Boot.
+config SPL_SYS_DCACHE_OFF
+ bool "Do not enable dcache in SPL"
+ depends on SPL
+ default n
+ help
+ Do not enable data cache in SPL.
+
menuconfig ARC_DBG
bool "ARC debugging"
default n
diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S
index 84959b41bd..8c744f5be7 100644
--- a/arch/arc/lib/start.S
+++ b/arch/arc/lib/start.S
@@ -16,7 +16,7 @@ ENTRY(_start)
lr r5, [ARC_BCR_IC_BUILD]
breq r5, 0, 1f ; I$ doesn't exist
lr r5, [ARC_AUX_IC_CTRL]
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
bclr r5, r5, 0 ; 0 - Enable, 1 is Disable
#else
bset r5, r5, 0 ; I$ exists, but is not used
@@ -37,7 +37,7 @@ ENTRY(_start)
breq r5, 0, 1f ; D$ doesn't exist
lr r5, [ARC_AUX_DC_CTRL]
bclr r5, r5, 6 ; Invalidate (discard w/o wback)
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
bclr r5, r5, 0 ; Enable (+Inv)
#else
bset r5, r5, 0 ; Disable (+Inv)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1eeac28b61..504769ca5a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -80,12 +80,26 @@ config SYS_ICACHE_OFF
help
Do not enable instruction cache in U-Boot.
+config SPL_SYS_ICACHE_OFF
+ bool "Do not enable icache in SPL"
+ depends on SPL
+ default n
+ help
+ Do not enable instruction cache in SPL.
+
config SYS_DCACHE_OFF
bool "Do not enable dcache"
default n
help
Do not enable data cache in U-Boot.
+config SPL_SYS_DCACHE_OFF
+ bool "Do not enable dcache in SPL"
+ depends on SPL
+ default n
+ help
+ Do not enable data cache in SPL.
+
config SYS_ARM_CACHE_CP15
bool "CP15 based cache enabling support"
help
diff --git a/arch/arm/cpu/arm11/cpu.c b/arch/arm/cpu/arm11/cpu.c
index 4aa704b9ee..8aee1539a9 100644
--- a/arch/arm/cpu/arm11/cpu.c
+++ b/arch/arm/cpu/arm11/cpu.c
@@ -51,7 +51,7 @@ static void cache_flush(void)
asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void invalidate_dcache_all(void)
{
asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
@@ -87,7 +87,7 @@ void flush_dcache_range(unsigned long start, unsigned long
stop)
asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
}
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
void invalidate_dcache_all(void)
{
}
@@ -95,15 +95,15 @@ void invalidate_dcache_all(void)
void flush_dcache_all(void)
{
}
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
void enable_caches(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable();
#endif
}
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
index 22a55f52e0..16eea693d1 100644
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -6,7 +6,7 @@
#include <linux/types.h>
#include <common.h>
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void invalidate_dcache_all(void)
{
asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
@@ -46,7 +46,7 @@ void flush_dcache_range(unsigned long start, unsigned long
stop)
asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
}
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
void invalidate_dcache_all(void)
{
}
@@ -54,7 +54,7 @@ void invalidate_dcache_all(void)
void flush_dcache_all(void)
{
}
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
/*
* Stub implementations for l2 cache operations
@@ -66,7 +66,7 @@ __weak void l2_cache_disable(void) {}
__weak void invalidate_l2_cache(void) {}
#endif
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
/* Invalidate entire I-cache and branch predictor array */
void invalidate_icache_all(void)
{
@@ -80,10 +80,10 @@ void invalidate_icache_all(void) {}
void enable_caches(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable();
#endif
}
diff --git a/arch/arm/cpu/arm926ejs/cpu.c b/arch/arm/cpu/arm926ejs/cpu.c
index c3f1ee1fd1..d7cffe8b69 100644
--- a/arch/arm/cpu/arm926ejs/cpu.c
+++ b/arch/arm/cpu/arm926ejs/cpu.c
@@ -44,7 +44,7 @@ int cleanup_before_linux (void)
/* flush I/D-cache */
static void cache_flush (void)
{
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
unsigned long i = 0;
asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index 1045673292..ff592ba810 100644
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -84,7 +84,7 @@ flush_dcache:
/*
* disable MMU and D cache
- * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
+ * enable I cache if SYS_ICACHE_OFF is not defined
*/
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
@@ -95,7 +95,7 @@ flush_dcache:
bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
#endif
orr r0, r0, #0x00000002 /* set bit 1 (A) Align */
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
#endif
mcr p15, 0, r0, c1, c0, 0
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index 99484c2636..0dc4ebf694 100644
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -12,7 +12,7 @@
#define ARMV7_DCACHE_INVAL_RANGE 1
#define ARMV7_DCACHE_CLEAN_INVAL_RANGE 2
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/* Asm functions from cache_v7_asm.S */
void v7_flush_dcache_all(void);
@@ -149,7 +149,7 @@ void mmu_page_table_flush(unsigned long start, unsigned
long stop)
flush_dcache_range(start, stop);
v7_inval_tlb();
}
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
void invalidate_dcache_all(void)
{
}
@@ -177,9 +177,9 @@ void mmu_page_table_flush(unsigned long start, unsigned
long stop)
void arm_init_domains(void)
{
}
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
/* Invalidate entire I-cache and branch predictor array */
void invalidate_icache_all(void)
{
diff --git a/arch/arm/cpu/armv7/iproc-common/hwinit-common.c
b/arch/arm/cpu/armv7/iproc-common/hwinit-common.c
index 8bf06a3e48..70431ecf6b 100644
--- a/arch/arm/cpu/armv7/iproc-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/iproc-common/hwinit-common.c
@@ -5,7 +5,7 @@
#include <common.h>
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/cpu/armv7/kona-common/hwinit-common.c
b/arch/arm/cpu/armv7/kona-common/hwinit-common.c
index 8783893cf6..10e7488879 100644
--- a/arch/arm/cpu/armv7/kona-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/kona-common/hwinit-common.c
@@ -6,7 +6,7 @@
#include <common.h>
#include <linux/sizes.h>
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index 7c4018ed11..ecf9e86985 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -26,7 +26,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/*
* Bit[1] of the descriptor indicates the descriptor type,
@@ -215,7 +215,7 @@ void enable_caches(void)
invalidate_dcache_all();
set_cr(get_cr() | CR_C);
}
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
uint get_svr(void)
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 0cb6dd39cc..dcb4195d7b 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -97,7 +97,7 @@ ENTRY(c_runtime_cpu_setup)
/*
* If I-cache is enabled invalidate it
*/
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
mcr p15, 0, r0, c7, c10, 4 @ DSB
mcr p15, 0, r0, c7, c5, 4 @ ISB
@@ -155,7 +155,7 @@ ENTRY(cpu_init_cp15)
bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
-#ifdef CONFIG_SYS_ICACHE_OFF
+#if CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
#else
orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
diff --git a/arch/arm/cpu/armv7/vf610/generic.c
b/arch/arm/cpu/armv7/vf610/generic.c
index 90fa695e98..f962903484 100644
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -360,7 +360,7 @@ int get_clocks(void)
return 0;
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c
index 815e623c29..1106bead41 100644
--- a/arch/arm/cpu/armv7m/cache.c
+++ b/arch/arm/cpu/armv7m/cache.c
@@ -54,7 +54,7 @@ enum cache_action {
FLUSH_INVAL_SET_WAY, /* d-cache clean & invalidate by set/ways */
};
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
struct dcache_config {
u32 ways;
u32 sets;
@@ -292,7 +292,7 @@ void invalidate_dcache_all(void)
}
#endif
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
void invalidate_icache_all(void)
{
@@ -349,10 +349,10 @@ int icache_status(void)
void enable_caches(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable();
#endif
}
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 038405173e..e6ab584e9d 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -13,7 +13,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/*
* With 4k page granule, a virtual address is split into 4 lookup parts
@@ -647,7 +647,7 @@ void mmu_change_region_attr(phys_addr_t addr, size_t siz,
u64 attrs)
__asm_invalidate_tlb_all();
}
-#else /* CONFIG_SYS_DCACHE_OFF */
+#else /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
/*
* For SPL builds, we may want to not have dcache enabled. Any real U-Boot
@@ -684,9 +684,9 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start,
size_t size,
{
}
-#endif /* CONFIG_SYS_DCACHE_OFF */
+#endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
void icache_enable(void)
{
@@ -710,7 +710,7 @@ void invalidate_icache_all(void)
__asm_invalidate_l3_icache();
}
-#else /* CONFIG_SYS_ICACHE_OFF */
+#else /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
void icache_enable(void)
{
@@ -729,7 +729,7 @@ void invalidate_icache_all(void)
{
}
-#endif /* CONFIG_SYS_ICACHE_OFF */
+#endif /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
/*
* Enable dCache & iCache, whether cache is actually enabled
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 978d46b32f..12d709e23e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -388,7 +388,7 @@ void cpu_name(char *name)
strcpy(name, "unknown");
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/*
* To start MMU before DDR is available, we create MMU table in SRAM.
* The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
@@ -611,7 +611,7 @@ void enable_caches(void)
icache_enable();
dcache_enable();
}
-#endif /* CONFIG_SYS_DCACHE_OFF */
+#endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
#ifdef CONFIG_TFABOOT
enum boot_src __get_boot_src(u32 porsr1)
diff --git a/arch/arm/cpu/armv8/s32v234/cpu.c b/arch/arm/cpu/armv8/s32v234/cpu.c
index 1fa6841eaf..b4cb67a66a 100644
--- a/arch/arm/cpu/armv8/s32v234/cpu.c
+++ b/arch/arm/cpu/armv8/s32v234/cpu.c
@@ -16,7 +16,7 @@ u32 cpu_mask(void)
return readl(MC_ME_CS);
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#define S32V234_IRAM_BASE 0x3e800000UL
#define S32V234_IRAM_SIZE 0x800000UL
diff --git a/arch/arm/cpu/pxa/cache.c b/arch/arm/cpu/pxa/cache.c
index 8b932b10e1..5cd4a9524b 100644
--- a/arch/arm/cpu/pxa/cache.c
+++ b/arch/arm/cpu/pxa/cache.c
@@ -6,7 +6,7 @@
#include <linux/types.h>
#include <common.h>
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void invalidate_dcache_all(void)
{
/* Flush/Invalidate I cache */
@@ -35,7 +35,7 @@ void flush_dcache_range(unsigned long start, unsigned long
stop)
{
return invalidate_dcache_range(start, stop);
}
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
void invalidate_dcache_all(void)
{
}
@@ -43,7 +43,7 @@ void invalidate_dcache_all(void)
void flush_dcache_all(void)
{
}
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
/*
* Stub implementations for l2 cache operations
diff --git a/arch/arm/cpu/pxa/pxa2xx.c b/arch/arm/cpu/pxa/pxa2xx.c
index b9fd41ece2..0b28f0a3ef 100644
--- a/arch/arm/cpu/pxa/pxa2xx.c
+++ b/arch/arm/cpu/pxa/pxa2xx.c
@@ -286,10 +286,10 @@ void reset_cpu(ulong ignored)
void enable_caches(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable();
#endif
}
diff --git a/arch/arm/include/asm/global_data.h
b/arch/arm/include/asm/global_data.h
index c3ee5f0c7b..a81b1061df 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -35,7 +35,7 @@ struct arch_global_data {
unsigned int tbl;
unsigned long lastinc;
unsigned long long timer_reset_value;
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
unsigned long tlb_addr;
unsigned long tlb_size;
#if defined(CONFIG_ARM64)
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 0688f1e6a6..b2913e8165 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -10,7 +10,7 @@
#include <linux/compiler.h>
#include <asm/armv7_mpu.h>
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
DECLARE_GLOBAL_DATA_PTR;
@@ -246,7 +246,7 @@ static void cache_disable(uint32_t cache_bit)
}
#endif
-#ifdef CONFIG_SYS_ICACHE_OFF
+#if CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
void icache_enable (void)
{
return;
@@ -278,7 +278,7 @@ int icache_status(void)
}
#endif
-#ifdef CONFIG_SYS_DCACHE_OFF
+#if CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void dcache_enable (void)
{
return;
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 565fbbe109..449544d11c 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -87,7 +87,7 @@ void noncached_init(void)
noncached_end = end;
noncached_next = start;
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF);
#endif
}
diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c
index 589e16c5ad..2ae9a43b4e 100644
--- a/arch/arm/mach-exynos/soc.c
+++ b/arch/arm/mach-exynos/soc.c
@@ -25,7 +25,7 @@ void reset_cpu(ulong addr)
#endif
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-imx/cache.c b/arch/arm/mach-imx/cache.c
index 75e1f54c6a..a605942503 100644
--- a/arch/arm/mach-imx/cache.c
+++ b/arch/arm/mach-imx/cache.c
@@ -37,7 +37,7 @@ static void enable_ca7_smp(void)
}
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 2c425357b5..53f9a8735a 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -446,7 +446,7 @@ void enable_caches(void)
dcache_enable();
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
u64 get_page_table_size(void)
{
u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
diff --git a/arch/arm/mach-imx/mx5/soc.c b/arch/arm/mach-imx/mx5/soc.c
index 43d6c08b42..bbb335e275 100644
--- a/arch/arm/mach-imx/mx5/soc.c
+++ b/arch/arm/mach-imx/mx5/soc.c
@@ -62,7 +62,7 @@ u32 __weak get_board_rev(void)
}
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c
index f43b3dcbfa..3dee300d77 100644
--- a/arch/arm/mach-keystone/init.c
+++ b/arch/arm/mach-keystone/init.c
@@ -204,7 +204,7 @@ void reset_cpu(ulong addr)
void enable_caches(void)
{
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
#endif
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 0777a0c998..bb01eab80e 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -34,7 +34,7 @@ obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o
endif
endif
-ifeq ($(CONFIG_SYS_DCACHE_OFF),)
+ifeq ($(CONFIG_$(SPL_TPL_)SYS_DCACHE_OFF),)
obj-y += omap-cache.o
endif
diff --git a/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S
b/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S
index 6dc92a6bfa..32de9d3d4f 100644
--- a/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S
+++ b/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S
@@ -16,7 +16,7 @@
.arch_extension sec
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
.global flush_dcache_range
#endif
@@ -79,7 +79,7 @@ ENTRY(omap_smc_sec_cpu1)
push {r4, r5, lr}
ldr r4, =omap_smc_sec_cpu1_args
stm r4, {r0,r1,r2,r3} @ Save args to memory
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
mov r0, r4
mov r1, #CONFIG_SYS_CACHELINE_SIZE
add r1, r0, r1 @ dcache is not enabled on CPU1, so
@@ -109,7 +109,7 @@ ENDPROC(omap_smc_sec_cpu1)
*/
.section .data
omap_smc_sec_cpu1_args:
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
.balign CONFIG_SYS_CACHELINE_SIZE
.rept CONFIG_SYS_CACHELINE_SIZE/4
.word 0
diff --git a/arch/arm/mach-omap2/sec-common.c b/arch/arm/mach-omap2/sec-common.c
index 600a31280c..b45d3ee544 100644
--- a/arch/arm/mach-omap2/sec-common.c
+++ b/arch/arm/mach-omap2/sec-common.c
@@ -333,7 +333,7 @@ int secure_tee_install(u32 addr)
debug("tee_info.tee_arg0 = %08X\n", tee_info.tee_arg0);
debug("tee_file_size = %d\n", tee_file_size);
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
flush_dcache_range(
rounddown((u32)loadptr, ARCH_DMA_MINALIGN),
roundup((u32)loadptr + tee_file_size, ARCH_DMA_MINALIGN));
@@ -356,7 +356,7 @@ int secure_tee_install(u32 addr)
/* Reuse the tee_info buffer for SMC params */
smc_cpu1_params = (u32 *)&tee_info;
smc_cpu1_params[0] = 0;
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
flush_dcache_range((u32)smc_cpu1_params, (u32)smc_cpu1_params +
roundup(sizeof(u32), ARCH_DMA_MINALIGN));
#endif
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index aa5be52dfd..499b3cdd43 100644
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -17,7 +17,7 @@ int arch_cpu_init(void)
/* R-Car Gen3 D-cache is enabled in memmap-gen3.c */
#ifndef CONFIG_RCAR_GEN3
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
dcache_enable();
diff --git a/arch/arm/mach-rockchip/rk3036-board.c
b/arch/arm/mach-rockchip/rk3036-board.c
index 872bed9606..a9a44539b5 100644
--- a/arch/arm/mach-rockchip/rk3036-board.c
+++ b/arch/arm/mach-rockchip/rk3036-board.c
@@ -48,7 +48,7 @@ int dram_init(void)
}
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-rockchip/rk3128-board.c
b/arch/arm/mach-rockchip/rk3128-board.c
index 7fd667a0b8..2c28099a75 100644
--- a/arch/arm/mach-rockchip/rk3128-board.c
+++ b/arch/arm/mach-rockchip/rk3128-board.c
@@ -57,7 +57,7 @@ int dram_init_banksize(void)
return 0;
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-rockchip/rk3188-board.c
b/arch/arm/mach-rockchip/rk3188-board.c
index 3802395bc0..e32bd922e8 100644
--- a/arch/arm/mach-rockchip/rk3188-board.c
+++ b/arch/arm/mach-rockchip/rk3188-board.c
@@ -75,7 +75,7 @@ err:
#endif
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-rockchip/rk322x-board.c
b/arch/arm/mach-rockchip/rk322x-board.c
index 5659248178..8627deb62a 100644
--- a/arch/arm/mach-rockchip/rk322x-board.c
+++ b/arch/arm/mach-rockchip/rk322x-board.c
@@ -85,7 +85,7 @@ int dram_init_banksize(void)
return 0;
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-rockchip/rk3288-board.c
b/arch/arm/mach-rockchip/rk3288-board.c
index 9c4f7f219f..9feb823722 100644
--- a/arch/arm/mach-rockchip/rk3288-board.c
+++ b/arch/arm/mach-rockchip/rk3288-board.c
@@ -186,7 +186,7 @@ err:
#endif
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-rockchip/rv1108/rv1108.c
b/arch/arm/mach-rockchip/rv1108/rv1108.c
index 33596f628c..66aeb3ffcc 100644
--- a/arch/arm/mach-rockchip/rv1108/rv1108.c
+++ b/arch/arm/mach-rockchip/rv1108/rv1108.c
@@ -6,7 +6,7 @@
#include <common.h>
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-s5pc1xx/cache.c b/arch/arm/mach-s5pc1xx/cache.c
index 12c9d7ce3a..0b879b545d 100644
--- a/arch/arm/mach-s5pc1xx/cache.c
+++ b/arch/arm/mach-s5pc1xx/cache.c
@@ -9,7 +9,7 @@
#include <common.h>
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
dcache_enable();
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index ec8339e045..8b311137f5 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -48,10 +48,10 @@ int dram_init(void)
void enable_caches(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable();
#endif
}
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index c6dd7b8e54..7f5b633e01 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -300,7 +300,7 @@ void reset_cpu(ulong addr)
#endif
}
-#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c
index f8fc042a1d..4e159075d3 100644
--- a/arch/arm/mach-tegra/board.c
+++ b/arch/arm/mach-tegra/board.c
@@ -226,7 +226,7 @@ U_BOOT_DEVICE(ns16550_com1) = {
};
#endif
-#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c
index a3422cd5cf..e5f557716b 100644
--- a/arch/arm/mach-zynq/cpu.c
+++ b/arch/arm/mach-zynq/cpu.c
@@ -83,7 +83,7 @@ void reset_cpu(ulong addr)
;
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/nds32/Kconfig b/arch/nds32/Kconfig
index 89d8af5142..feeec4448d 100644
--- a/arch/nds32/Kconfig
+++ b/arch/nds32/Kconfig
@@ -22,12 +22,26 @@ config SYS_ICACHE_OFF
help
Do not enable instruction cache in U-Boot.
+config SPL_SYS_ICACHE_OFF
+ bool "Do not enable icache in SPL"
+ depends on SPL
+ default n
+ help
+ Do not enable instruction cache in SPL.
+
config SYS_DCACHE_OFF
bool "Do not enable dcache"
default n
help
Do not enable data cache in U-Boot.
+config SPL_SYS_DCACHE_OFF
+ bool "Do not enable dcache in SPL"
+ depends on SPL
+ default n
+ help
+ Do not enable data cache in SPL.
+
source "board/AndesTech/adp-ag101p/Kconfig"
source "board/AndesTech/adp-ae3xx/Kconfig"
diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S
index 4e6a0e7a31..691888157f 100644
--- a/arch/nds32/cpu/n1213/start.S
+++ b/arch/nds32/cpu/n1213/start.S
@@ -129,7 +129,7 @@ set_ivb:
mfsr $r1, $mr8
and $r1, $r1, $r0
mtsr $r1, $mr8
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
/*
* MMU_CTL NTC0 Cacheable/Write-Back
*/
@@ -139,7 +139,7 @@ set_ivb:
mtsr $r1, $mr0
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#ifdef CONFIG_ARCH_MAP_SYSMEM
/*
* MMU_CTL NTC1 Non-cacheable
@@ -158,14 +158,14 @@ set_ivb:
#endif
#endif
-#if !defined(CONFIG_SYS_ICACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
li $r0, 0x1
mfsr $r1, $mr8
or $r1, $r1, $r0
mtsr $r1, $mr8
#endif
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
li $r0, 0x2
mfsr $r1, $mr8
or $r1, $r1, $r0
diff --git a/arch/nds32/lib/cache.c b/arch/nds32/lib/cache.c
index 3e5aa7cda8..27065136dd 100644
--- a/arch/nds32/lib/cache.c
+++ b/arch/nds32/lib/cache.c
@@ -6,7 +6,7 @@
*/
#include <common.h>
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
static inline unsigned long CACHE_SET(unsigned char cache)
{
if (cache == ICACHE)
@@ -38,7 +38,7 @@ static inline unsigned long CACHE_LINE_SIZE(enum cache_t
cache)
}
#endif
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
void invalidate_icache_all(void)
{
unsigned long end, line_size;
@@ -133,7 +133,7 @@ int icache_status(void)
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void dcache_wbinval_all(void)
{
unsigned long end, line_size;
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index b22f00ad0b..54362d7a45 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -25,12 +25,26 @@ config SYS_ICACHE_OFF
help
Do not enable instruction cache in U-Boot.
+config SPL_SYS_ICACHE_OFF
+ bool "Do not enable icache in SPL"
+ depends on SPL
+ default n
+ help
+ Do not enable instruction cache in SPL.
+
config SYS_DCACHE_OFF
bool "Do not enable dcache"
default n
help
Do not enable data cache in U-Boot.
+config SPL_SYS_DCACHE_OFF
+ bool "Do not enable dcache in SPL"
+ depends on SPL
+ default n
+ help
+ Do not enable data cache in SPL.
+
# board-specific options below
source "board/AndesTech/ax25-ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
index 228fc55f56..cd95058d9d 100644
--- a/arch/riscv/cpu/ax25/cache.c
+++ b/arch/riscv/cpu/ax25/cache.c
@@ -30,7 +30,7 @@ void invalidate_dcache_range(unsigned long start, unsigned
long end)
void icache_enable(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"csrr t1, mcache_ctl\n\t"
@@ -43,7 +43,7 @@ void icache_enable(void)
void icache_disable(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"fence.i\n\t"
@@ -57,7 +57,7 @@ void icache_disable(void)
void dcache_enable(void)
{
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"csrr t1, mcache_ctl\n\t"
@@ -70,7 +70,7 @@ void dcache_enable(void)
void dcache_disable(void)
{
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"fence\n\t"
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index c8b72ebf05..f437b98409 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -22,12 +22,26 @@ config SYS_ICACHE_OFF
help
Do not enable instruction cache in U-Boot.
+config SPL_SYS_ICACHE_OFF
+ bool "Do not enable icache in SPL"
+ depends on SPL
+ default n
+ help
+ Do not enable instruction cache in SPL.
+
config SYS_DCACHE_OFF
bool "Do not enable dcache"
default n
help
Do not enable data cache in U-Boot.
+config SPL_SYS_DCACHE_OFF
+ bool "Do not enable dcache in SPL"
+ depends on SPL
+ default n
+ help
+ Do not enable data cache in SPL.
+
source "board/cadence/xtfpga/Kconfig"
endmenu
diff --git a/arch/xtensa/cpu/start.S b/arch/xtensa/cpu/start.S
index 0fafb1c4f8..38d2fa2fe1 100644
--- a/arch/xtensa/cpu/start.S
+++ b/arch/xtensa/cpu/start.S
@@ -164,18 +164,19 @@ _start:
* enable data/instruction cache for relocated image.
*/
#if XCHAL_HAVE_SPANNING_WAY && \
- !(defined(CONFIG_SYS_DCACHE_OFF) && defined(CONFIG_SYS_ICACHE_OFF))
+ !(CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && \
+ CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
srli a7, a4, 29
slli a7, a7, 29
addi a7, a7, XCHAL_SPANNING_WAY
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
rdtlb1 a8, a7
srli a8, a8, 4
slli a8, a8, 4
addi a8, a8, CA_WRITEBACK
wdtlb a8, a7
#endif
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
ritlb1 a8, a7
srli a8, a8, 4
slli a8, a8, 4
diff --git a/board/st/stih410-b2260/board.c b/board/st/stih410-b2260/board.c
index b4fc8f3ce1..111e64b995 100644
--- a/board/st/stih410-b2260/board.c
+++ b/board/st/stih410-b2260/board.c
@@ -26,7 +26,7 @@ int dram_init_banksize(void)
return 0;
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index cbeba6ba28..f576e226ee 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -321,7 +321,7 @@ static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc,
print_eths();
#endif
print_baudrate();
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
print_num("TLB addr", gd->arch.tlb_addr);
#endif
print_num("relocaddr", gd->relocaddr);
diff --git a/common/board_f.c b/common/board_f.c
index 7ef20f2042..c25eb188fb 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -381,7 +381,7 @@ static int reserve_round_4k(void)
#ifdef CONFIG_ARM
__weak int reserve_mmu(void)
{
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
/* reserve TLB table */
gd->arch.tlb_size = PGTABLE_SIZE;
gd->relocaddr -= gd->arch.tlb_size;
diff --git a/common/lcd.c b/common/lcd.c
index cd630405d4..95526b1e17 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -61,7 +61,7 @@ void lcd_sync(void)
* architectures do not actually implement it. Is there a way to find
* out whether it exists? For now, ARM is safe.
*/
-#if defined(CONFIG_ARM) && !defined(CONFIG_SYS_DCACHE_OFF)
+#if defined(CONFIG_ARM) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
int line_length;
if (lcd_flush_dcache)
diff --git a/configs/bitmain_antminer_s9_defconfig
b/configs/bitmain_antminer_s9_defconfig
index 63acd28c7e..3787a9573a 100644
--- a/configs/bitmain_antminer_s9_defconfig
+++ b/configs/bitmain_antminer_s9_defconfig
@@ -3,6 +3,7 @@ CONFIG_SYS_VENDOR="bitmain"
CONFIG_SYS_BOARD="antminer_s9"
CONFIG_SYS_CONFIG_NAME="bitmain_antminer_s9"
CONFIG_ARCH_ZYNQ=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_ENV_OFFSET=0x300000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
index 989dc445d0..9a962b3da7 100644
--- a/configs/imx8mq_evk_defconfig
+++ b/configs/imx8mq_evk_defconfig
@@ -1,5 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_IMX8MQ_EVK=y
diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig
index 2fb2fdf7ff..6bee2d1024 100644
--- a/configs/imx8qxp_mek_defconfig
+++ b/configs/imx8qxp_mek_defconfig
@@ -1,5 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_IMX8=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x80020000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig
index 005b6e9044..ffe50b1fd7 100644
--- a/configs/smartweb_defconfig
+++ b/configs/smartweb_defconfig
@@ -2,6 +2,8 @@ CONFIG_ARM=y
CONFIG_SPL_SYS_THUMB_BUILD=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x23000000
CONFIG_TARGET_SMARTWEB=y
diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig
index 896232a715..5616b3e23a 100644
--- a/configs/syzygy_hub_defconfig
+++ b/configs/syzygy_hub_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
CONFIG_SYS_VENDOR="opalkelly"
CONFIG_SYS_CONFIG_NAME="syzygy_hub"
CONFIG_ARCH_ZYNQ=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
index 0da77d8c94..684a0ede73 100644
--- a/configs/taurus_defconfig
+++ b/configs/taurus_defconfig
@@ -2,6 +2,8 @@ CONFIG_ARM=y
CONFIG_SPL_SYS_THUMB_BUILD=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_AT91=y
CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds"
CONFIG_SYS_TEXT_BASE=0x21000000
diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig
index b55885669d..bb8d37a370 100644
--- a/configs/topic_miami_defconfig
+++ b/configs/topic_miami_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
CONFIG_SYS_VENDOR="topic"
CONFIG_SYS_CONFIG_NAME="topic_miami"
CONFIG_ARCH_ZYNQ=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
diff --git a/configs/topic_miamilite_defconfig
b/configs/topic_miamilite_defconfig
index 6983245173..87af8c81d3 100644
--- a/configs/topic_miamilite_defconfig
+++ b/configs/topic_miamilite_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
CONFIG_SYS_VENDOR="topic"
CONFIG_SYS_CONFIG_NAME="topic_miami"
CONFIG_ARCH_ZYNQ=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
diff --git a/configs/topic_miamiplus_defconfig
b/configs/topic_miamiplus_defconfig
index 89461ee6d2..874ca8a746 100644
--- a/configs/topic_miamiplus_defconfig
+++ b/configs/topic_miamiplus_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
CONFIG_SYS_VENDOR="topic"
CONFIG_SYS_CONFIG_NAME="topic_miami"
CONFIG_ARCH_ZYNQ=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig
index f4db2df8a4..2d0ecb1fdd 100644
--- a/configs/zynq_cse_nand_defconfig
+++ b/configs/zynq_cse_nand_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="zynq_cse"
CONFIG_ARCH_ZYNQ=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x100000
CONFIG_ENV_SIZE=0x190
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig
index 8f1df5f0b1..23e15da651 100644
--- a/configs/zynq_cse_nor_defconfig
+++ b/configs/zynq_cse_nor_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="zynq_cse"
CONFIG_ARCH_ZYNQ=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0xFFFC0000
CONFIG_ENV_SIZE=0x190
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig
index 1edd0cbf4b..b81198b339 100644
--- a/configs/zynq_cse_qspi_defconfig
+++ b/configs/zynq_cse_qspi_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="zynq_cse"
CONFIG_ARCH_ZYNQ=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0xFFFC0000
CONFIG_ENV_SIZE=0x190
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
index 017cc89a89..ac589feeb7 100644
--- a/drivers/dma/apbh_dma.c
+++ b/drivers/dma/apbh_dma.c
@@ -81,7 +81,7 @@ static int mxs_dma_read_semaphore(int channel)
return tmp;
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void mxs_dma_flush_desc(struct mxs_dma_desc *desc)
{
uint32_t addr;
diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c
index be4ee2c7f8..b93d77a395 100644
--- a/drivers/mtd/nand/raw/mxs_nand.c
+++ b/drivers/mtd/nand/raw/mxs_nand.c
@@ -50,7 +50,7 @@ struct nand_ecclayout fake_ecc_layout;
/*
* Cache management functions
*/
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
{
uint32_t addr = (uint32_t)info->data_buf;
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 9f1c5af46e..590e756f5c 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -241,7 +241,7 @@ struct eqos_tegra186_regs {
*/
#if EQOS_DESCRIPTOR_SIZE < ARCH_DMA_MINALIGN
#if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
- !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86)
+ !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
#warning Cache line size is larger than descriptor size
#endif
#endif
diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index a78f3d233f..70dc362650 100644
--- a/drivers/net/rtl8169.c
+++ b/drivers/net/rtl8169.c
@@ -301,7 +301,7 @@ static unsigned char rxdata[RX_BUF_LEN];
*/
#if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN
#if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
- !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86)
+ !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
#warning cache-line size is larger than descriptor size
#endif
#endif
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 4646f2ba4e..741c58453f 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -34,7 +34,8 @@
# error "Please define CONFIG_SH_ETHER_PHY_ADDR"
#endif
-#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF)
+#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && \
+ !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#define flush_cache_wback(addr, len) \
flush_dcache_range((u32)addr, \
(u32)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c
index 14aac88d6d..b19bfb4f2f 100644
--- a/drivers/video/video-uclass.c
+++ b/drivers/video/video-uclass.c
@@ -149,7 +149,7 @@ void video_sync(struct udevice *vid, bool force)
* architectures do not actually implement it. Is there a way to find
* out whether it exists? For now, ARM is safe.
*/
-#if defined(CONFIG_ARM) && !defined(CONFIG_SYS_DCACHE_OFF)
+#if defined(CONFIG_ARM) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
struct video_priv *priv = dev_get_uclass_priv(vid);
if (priv->flush_dcache) {
diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h
index aaecf6f053..bdfd82de2c 100644
--- a/include/configs/imx8mq_evk.h
+++ b/include/configs/imx8mq_evk.h
@@ -36,8 +36,6 @@
#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
#define CONFIG_MALLOC_F_ADDR 0x182000
diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h
index 18ea5a8fb6..e847158b92 100644
--- a/include/configs/imx8qxp_mek.h
+++ b/include/configs/imx8qxp_mek.h
@@ -23,8 +23,6 @@
#define CONFIG_SYS_SPL_MALLOC_START 0x00120000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
#define CONFIG_SERIAL_LPUART_BASE 0x5a060000
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_MALLOC_F_ADDR 0x00120000
#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h
index b8dcaa1036..34970ba7a2 100644
--- a/include/configs/mx7ulp_evk.h
+++ b/include/configs/mx7ulp_evk.h
@@ -168,7 +168,7 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#define CONFIG_CMD_CACHE
#endif
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index 0d0c6bdc69..776d7d7970 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -216,11 +216,6 @@
#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR)
#define CONFIG_SYS_AT91_PLLB 0x10483f0e
-#if defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
-#endif
-
#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS
#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index c3353d74a9..ce784f90ab 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -21,10 +21,6 @@
#include <asm/hardware.h>
#include <linux/sizes.h>
-#if defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
-#endif
/*
* Warning: changing CONFIG_SYS_TEXT_BASE requires
* adapting the initial boot program.
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 523d4da56b..143dc7bb22 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -284,11 +284,6 @@
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#endif
-/* Disable dcache for SPL just for sure */
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_DCACHE_OFF
-#endif
-
/* Address in RAM where the parameters must be copied by SPL. */
#define CONFIG_SYS_SPL_ARGS_ADDR 0x10000000
--
2.21.0.rc2
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