On Tue, 2019-05-07 at 22:00 +0200, Simon Goldschmidt wrote:
>
> On 07.05.19 19:25, Andreas Dannenberg wrote:
> >
[...]
> >
> > While I also have a working solution based on the existing FS
> > loader
> > framework this has its own challenges, namely by its very nature
> > only
> > addressing a subset of our use cases (no eMMC/SD RAW boot support
> > for
> > example),
IMO, it's actually not that hard to enhance RAW support, i think
minimal changes are required. I have attached the patches about an
example of loading RAW from QSPI that i have done locally last few week
ago.
> > being heavier on resource usage (needing to use ENV to pass
> > parameters),
ENV is optional, you can use DTS. For example loading FPGA bitstream
from QSPI RAW:
/* DTS */
/ {
+ aliases {
+ spi0 = &qspi;
+ };
+
+ fs_loader0: fs-loader {
+ u-boot,dm-pre-reloc;
+ compatible = "u-boot,fs-loader";
+ sfconfig = <0 0 100000000 3>;
+ };
+};
+
+&fpga_mgr {
+ u-boot,dm-pre-reloc;
+ firmware-loader = <&fs_loader0>;
+ altr,bitstream = "300000";
+};
> > and not addressing the need to probe the boot peripheral.
You can add more different probing method in function called
"fs_loader_probe". Current fs_loader supports block(sdmmc, emmc, etc...)
probing, and with
the patches attached support QSPI probing.
Another idea come to mind, we can use fs_loader for loading FIT boot
image into RAM, and boot from RAM with existing SPL loader framework,
but i'm not sure this implementation fit to your use case?
> > This particular framework works well for use cases requiring to
> > load
> > firmware from FS-based media once DDR is up and U-Boot is in a more
> > "initialized" state but it is not a one-fits all solution for very
> > early use in SPL board_init_f() accross different boot modes.
> And would it be an option to improve the loader (maybe dropping the
> "fs"
> from its name)? I think it's an "fs" loader because its idea has
> been
> copied from Linux. I think in U-Boot, it's more common to have things
> at
> a raw offset instead of a file system. Just thinking...
Current fs_loader only support filesystem, and i agree that it made
sense to remove the "fs" once it supports the RAW offset as well.
Thanks.
Regards,
TF
>
> And the current state of that fs_loader is like it is because it
> fits
> its single user (socfpga stratix 10), I think.
>
> Anyway, even if you do need yet another loader, would it make sense
> to
> create a common file instead of adding this in your arch/mach?
>
> Regards,
> Simon
>
> >
> >
> > Andreas Dannenberg (10):
> > mmc: k3_arasan: Allow driver to probe without PDs specified
> > spl: Allow skipping clearing BSS during relocation
> > spl: Make image loader infrastructure more universal
> > arm: K3: Introduce System Firmware loader framework
> > armV7R: K3: am654: Allow using SPL BSS pre-relocation
> > armv7R: K3: am654: Use full malloc implementation in SPL
> > armV7R: K3: am654: Load SYSFW binary and config from boot media
> > configs: am65x_evm_r5: All sysfw to be loaded via MMC
> > configs: am65x_hs_evm_r5: All sysfw to be loaded via MMC
> > configs: am65x_hs_evm: Add Support for eMMC boot
> >
> > Faiz Abbas (2):
> > configs: am65x_evm: Add Support for eMMC boot
> > am65x: README: Add eMMC layout and flash instructions
> >
> > Lokesh Vutla (1):
> > armv7R: dts: k3: am654: Update mmc nodes for loading sysfw
> >
> > arch/arm/dts/k3-am654-r5-base-board.dts | 18 ++
> > arch/arm/lib/crt0.S | 3 +
> > arch/arm/mach-k3/Kconfig | 40 +++
> > arch/arm/mach-k3/Makefile | 1 +
> > arch/arm/mach-k3/am6_init.c | 34 ++-
> > arch/arm/mach-k3/include/mach/sysfw-loader.h | 12 +
> > arch/arm/mach-k3/sysfw-loader.c | 263
> > +++++++++++++++++++
> > board/ti/am65x/Kconfig | 1 +
> > board/ti/am65x/README | 52 ++++
> > common/spl/Kconfig | 13 +
> > common/spl/spl_fit.c | 14 +
> > common/spl/spl_mmc.c | 76 ++++--
> > configs/am65x_evm_a53_defconfig | 2 +
> > configs/am65x_evm_r5_defconfig | 7 +-
> > configs/am65x_hs_evm_a53_defconfig | 2 +
> > configs/am65x_hs_evm_r5_defconfig | 7 +-
> > drivers/mmc/k3_arsan_sdhci.c | 16 +-
> > include/configs/am65x_evm.h | 30 ++-
> > include/spl.h | 26 ++
> > 19 files changed, 577 insertions(+), 40 deletions(-)
> > create mode 100644 arch/arm/mach-k3/include/mach/sysfw-loader.h
> > create mode 100644 arch/arm/mach-k3/sysfw-loader.c
> > From ff0fa68b8141fa7c83b3b42e7d6cf5a6bc27c980 Mon Sep 17 00:00:00 2001
From: Tien Fong Chee <tien.fong.c...@intel.com>
Date: Mon, 15 Apr 2019 14:02:44 +0800
Subject: [PATCH 01/10] misc: fs_loader: Add QSPI RAW partition loading support
Enhanced the generic firmware loader to support QSPI RAW partition
loading. This would enable FPGA configuration bitstream loading
from QSPI RAW partition to program FPGA.
Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com>
---
drivers/misc/fs_loader.c | 85 +++++++++++++++++++++++++++++++++++++++++-------
include/fs_loader.h | 35 ++++++++++++++++++++
2 files changed, 109 insertions(+), 11 deletions(-)
diff --git a/drivers/misc/fs_loader.c b/drivers/misc/fs_loader.c
index f42eeff8f6..638eb1e0d2 100644
--- a/drivers/misc/fs_loader.c
+++ b/drivers/misc/fs_loader.c
@@ -13,6 +13,7 @@
#include <mapmem.h>
#include <malloc.h>
#include <spl.h>
+#include <spi_flash.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -59,6 +60,11 @@ static int mount_ubifs(char *mtdpart, char *ubivol)
}
#endif
+__weak struct blk_desc *blk_get_by_device(struct udevice *dev)
+{
+ return NULL;
+}
+
static int select_fs_dev(struct device_platdata *plat)
{
int ret;
@@ -113,16 +119,26 @@ static int _request_firmware_prepare(struct udevice *dev,
const char *name, void *dbuf,
size_t size, u32 offset)
{
- if (!name || name[0] == '\0')
- return -EINVAL;
-
struct firmware *firmwarep = dev_get_priv(dev);
+ struct device_platdata *plat = dev->platdata;
+ char *endptr;
+ u32 fw_offset;
if (!firmwarep)
return -ENOMEM;
firmwarep->name = name;
- firmwarep->offset = offset;
+
+ if (plat->data_type == DATA_RAW) {
+ fw_offset = simple_strtoul(firmwarep->name, &endptr, 16);
+ if (firmwarep->name == endptr || *endptr != '\0')
+ return -EINVAL;
+
+ firmwarep->offset = fw_offset + offset;
+ } else {
+ firmwarep->offset = offset;
+ }
+
firmwarep->data = dbuf;
firmwarep->size = size;
@@ -139,7 +155,8 @@ static int fw_get_filesystem_firmware(struct udevice *dev)
{
loff_t actread;
char *storage_interface, *dev_part, *ubi_mtdpart, *ubi_volume;
- int ret;
+ int ret = 0;
+ struct device_platdata *plat = dev->platdata;
storage_interface = env_get("storage_interface");
dev_part = env_get("fw_dev_part");
@@ -159,7 +176,8 @@ static int fw_get_filesystem_firmware(struct udevice *dev)
else
ret = -ENODEV;
} else {
- ret = select_fs_dev(dev->platdata);
+ if (plat->data_type == DATA_FS)
+ ret = select_fs_dev(dev->platdata);
}
if (ret)
@@ -170,8 +188,18 @@ static int fw_get_filesystem_firmware(struct udevice *dev)
if (!firmwarep)
return -ENOMEM;
- ret = fs_read(firmwarep->name, (ulong)map_to_sysmem(firmwarep->data),
- firmwarep->offset, firmwarep->size, &actread);
+ if (plat->data_type == DATA_FS)
+ ret = fs_read(firmwarep->name,
+ (ulong)map_to_sysmem(firmwarep->data),
+ firmwarep->offset, firmwarep->size, &actread);
+ else if (plat->data_type == DATA_RAW) {
+#ifdef CONFIG_SPI_FLASH
+ ret = spi_flash_read_dm(plat->flash, firmwarep->offset,
+ firmwarep->size,
+ (void *)map_to_sysmem(firmwarep->data));
+ actread = firmwarep->size;
+#endif
+ }
if (ret) {
debug("Error: %d Failed to read %s from flash %lld != %zu.\n",
@@ -220,6 +248,7 @@ int request_firmware_into_buf(struct udevice *dev,
static int fs_loader_ofdata_to_platdata(struct udevice *dev)
{
u32 phandlepart[2];
+ u32 sfconfig[4];
ofnode fs_loader_node = dev_ofnode(dev);
@@ -239,6 +268,17 @@ static int fs_loader_ofdata_to_platdata(struct udevice *dev)
plat->ubivol = (char *)ofnode_read_string(
fs_loader_node, "ubivol");
+
+ if (!ofnode_read_u32_array(fs_loader_node, "sfconfig", sfconfig,
+ 4)) {
+ plat->data_type = DATA_RAW;
+ plat->sfconfig.bus = sfconfig[0];
+ plat->sfconfig.cs = sfconfig[1];
+ plat->sfconfig.speed = sfconfig[2];
+ plat->sfconfig.mode = sfconfig[3];
+ } else {
+ plat->data_type = DATA_FS;
+ }
}
return 0;
@@ -246,10 +286,33 @@ static int fs_loader_ofdata_to_platdata(struct udevice *dev)
static int fs_loader_probe(struct udevice *dev)
{
-#if CONFIG_IS_ENABLED(DM) && CONFIG_IS_ENABLED(BLK)
- int ret;
+ int ret = 0;
struct device_platdata *plat = dev->platdata;
+#ifdef CONFIG_SPI_FLASH
+ if (!plat->flash) {
+ debug("bus = %d\ncs = %d\nspeed= %d\nmode = %d\n",
+ plat->sfconfig.bus, plat->sfconfig.cs,
+ plat->sfconfig.speed, plat->sfconfig.mode);
+
+ ret = spi_flash_probe_bus_cs(plat->sfconfig.bus,
+ plat->sfconfig.cs,
+ plat->sfconfig.speed,
+ plat->sfconfig.mode,
+ &plat->flash);
+ if (ret) {
+ debug("fs_loader: Failed to initialize SPI flash at ");
+ debug("%u:%u (error %d)\n", plat->sfconfig.bus,
+ plat->sfconfig.cs, ret);
+ return -ENODEV;
+ }
+
+ if (!plat->flash)
+ return -EINVAL;
+ }
+#endif
+
+#if CONFIG_IS_ENABLED(DM) && CONFIG_IS_ENABLED(BLK)
if (plat->phandlepart.phandle) {
ofnode node = ofnode_get_by_phandle(plat->phandlepart.phandle);
struct udevice *parent_dev = NULL;
@@ -269,7 +332,7 @@ static int fs_loader_probe(struct udevice *dev)
}
#endif
- return 0;
+ return ret;
};
static const struct udevice_id fs_loader_ids[] = {
diff --git a/include/fs_loader.h b/include/fs_loader.h
index b728c06fcf..fc371272fa 100644
--- a/include/fs_loader.h
+++ b/include/fs_loader.h
@@ -23,6 +23,35 @@ struct phandle_part {
};
/**
+ * struct sf_config - A place for storing serial flash configuration
+ *
+ * This holds information about bus, chip-select, and speed and mode of a serial
+ * flash configuration.
+ *
+ * @bus: SPI bus number.
+ * @cs: SPI chip selection.
+ * @speed: Speed selection.
+ * @mode: SPI mode.
+ */
+struct sf_config {
+ u32 bus;
+ u32 cs;
+ u32 speed;
+ u32 mode;
+};
+
+/**
+ * enum data_flags - Flag to indicate data as RAW or as filesystem
+ *
+ * DATA_RAW: Data stored as RAW.
+ * DATA_FS: DATA stored as filesystem.
+ */
+enum data_flags {
+ DATA_RAW, /* Stored in raw */
+ DATA_FS, /* Stored within a file system */
+};
+
+/**
* struct phandle_part - A place for storing all supported storage devices
*
* This holds information about all supported storage devices for driver use.
@@ -30,11 +59,17 @@ struct phandle_part {
* @phandlepart: Attribute data for block device.
* @mtdpart: MTD partition for ubi partition.
* @ubivol: UBI volume-name for ubifsmount.
+ * @enum data_flags: Data type (RAW or filesystem).
+ * @struct sf_config: Serial flash configuration.
+ * @struct spi_flash: Information about a SPI flash.
*/
struct device_platdata {
struct phandle_part phandlepart;
char *mtdpart;
char *ubivol;
+ enum data_flags data_type;
+ struct sf_config sfconfig;
+ struct udevice *flash;
};
/**
--
2.13.0
From 1d7dc60d7b0afb01bd8d72932aeef392282cbb10 Mon Sep 17 00:00:00 2001
From: Tien Fong Chee <tien.fong.c...@intel.com>
Date: Mon, 15 Apr 2019 16:14:10 +0800
Subject: [PATCH 04/10] ARM: dts: socfpga: Add dts support for QSPI Arria 10
SoCDK
Enable dtb build for QSPI Arria 10 SoCDK.
Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/socfpga_arria10_socdk_qspi.dts | 61 +++
.../dts/socfpga_arria10_socdk_qspi_handoff.dtsi | 538 +++++++++++++++++++++
3 files changed, 600 insertions(+)
create mode 100644 arch/arm/dts/socfpga_arria10_socdk_qspi.dts
create mode 100644 arch/arm/dts/socfpga_arria10_socdk_qspi_handoff.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2a040b20a5..f377a1c2b2 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -214,6 +214,7 @@ dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_arria5_socdk.dtb \
+ socfpga_arria10_socdk_qspi.dtb \
socfpga_arria10_socdk_sdmmc.dtb \
socfpga_cyclone5_is1.dtb \
socfpga_cyclone5_socdk.dtb \
diff --git a/arch/arm/dts/socfpga_arria10_socdk_qspi.dts b/arch/arm/dts/socfpga_arria10_socdk_qspi.dts
new file mode 100644
index 0000000000..8a36cf8410
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_socdk_qspi.dts
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright (C) 2019 Intel Corporation
+ *
+ * These codes were based on handoffs
+ * generated from both Qsys and Quartus.
+ */
+
+/dts-v1/;
+#include "socfpga_arria10_socdk_qspi_handoff.dtsi"
+#include "socfpga_arria10_socdk.dtsi"
+
+/ {
+ aliases {
+ spi0 = &qspi;
+ };
+
+ fs_loader0: fs-loader {
+ u-boot,dm-pre-reloc;
+ compatible = "u-boot,fs-loader";
+ sfconfig = <0 0 100000000 3>;
+ };
+};
+
+&fpga_mgr {
+ u-boot,dm-pre-reloc;
+ firmware-loader = <&fs_loader0>;
+ altr,bitstream = "300000";
+};
+
+&l4_main_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&qspi_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&qspi {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+
+ flash0: n25q00a@0 {
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q00a", "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <100000000>;
+
+ page-size = <256>;
+ block-size = <16>; /* 2^16, 64KB */
+ cdns,page-size = <256>;
+ cdns,block-size = <16>;
+ cdns,read-delay = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+ };
+};
diff --git a/arch/arm/dts/socfpga_arria10_socdk_qspi_handoff.dtsi b/arch/arm/dts/socfpga_arria10_socdk_qspi_handoff.dtsi
new file mode 100644
index 0000000000..4c9717d62f
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_socdk_qspi_handoff.dtsi
@@ -0,0 +1,538 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright (C) 2019 Intel Corporation
+ *
+ * These codes were based on handoffs
+ * generated from both Qsys and Quartus.
+ */
+
+#include "socfpga_arria10.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "SOCFPGA Arria10 Dev Kit"; /* Bootloader setting: uboot.model */
+
+ /* Clock sources */
+ clocks {
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* Clock source: altera_arria10_hps_eosc1 */
+ altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 {
+ u-boot,dm-pre-reloc;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ clock-output-names = "altera_arria10_hps_eosc1-clk";
+ };
+
+ /* Clock source: altera_arria10_hps_cb_intosc_ls */
+ altera_arria10_hps_cb_intosc_ls:
+ altera_arria10_hps_cb_intosc_ls {
+ u-boot,dm-pre-reloc;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <60000000>;
+ clock-output-names =
+ "altera_arria10_hps_cb_intosc_ls-clk";
+ };
+
+ /* Clock source: altera_arria10_hps_f2h_free */
+ altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free {
+ u-boot,dm-pre-reloc;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ clock-output-names = "altera_arria10_hps_f2h_free-clk";
+ };
+ };
+
+ /*
+ * Driver: altera_arria10_soc_clock_manager_arria10_uboot_driver
+ * Version: 1.0
+ * Binding: device
+ */
+ i_clk_mgr: clock_manager@0xffd04000 {
+ u-boot,dm-pre-reloc;
+ compatible = "altr,socfpga-a10-clk-init";
+ reg = <0xffd04000 0x00000200>;
+ reg-names = "soc_clock_manager_OCP_SLV";
+
+ /*
+ * Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_mainpllgrp
+ */
+ mainpll {
+ u-boot,dm-pre-reloc;
+ /* Field: vco0.psrc */
+ vco0-psrc = <0>;
+ /* Field: vco1.denom */
+ vco1-denom = <1>;
+ /* Field: vco1.numer */
+ vco1-numer = <191>;
+ /* Field: mpuclk.cnt */
+ mpuclk-cnt = <0>;
+ /* Field: mpuclk.src */
+ mpuclk-src = <0>;
+ /* Field: nocclk.cnt */
+ nocclk-cnt = <0>;
+ /* Field: nocclk.src */
+ nocclk-src = <0>;
+ /* Field: cntr2clk.cnt */
+ cntr2clk-cnt = <900>;
+ /* Field: cntr3clk.cnt */
+ cntr3clk-cnt = <900>;
+ /* Field: cntr4clk.cnt */
+ cntr4clk-cnt = <900>;
+ /* Field: cntr5clk.cnt */
+ cntr5clk-cnt = <900>;
+ /* Field: cntr6clk.cnt */
+ cntr6clk-cnt = <900>;
+ /* Field: cntr7clk.cnt */
+ cntr7clk-cnt = <900>;
+ /* Field: cntr7clk.src */
+ cntr7clk-src = <0>;
+ /* Field: cntr8clk.cnt */
+ cntr8clk-cnt = <900>;
+ /* Field: cntr9clk.cnt */
+ cntr9clk-cnt = <900>;
+ /* Field: cntr9clk.src */
+ cntr9clk-src = <0>;
+ /* Field: cntr15clk.cnt */
+ cntr15clk-cnt = <900>;
+ /* Field: nocdiv.l4mainclk */
+ nocdiv-l4mainclk = <0>;
+ /* Field: nocdiv.l4mpclk */
+ nocdiv-l4mpclk = <0>;
+ /* Field: nocdiv.l4spclk */
+ nocdiv-l4spclk = <2>;
+ /* Field: nocdiv.csatclk */
+ nocdiv-csatclk = <0>;
+ /* Field: nocdiv.cstraceclk */
+ nocdiv-cstraceclk = <1>;
+ /* Field: nocdiv.cspdbgclk */
+ nocdiv-cspdbgclk = <1>;
+ };
+
+ /*
+ * Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_perpllgrp
+ */
+ perpll {
+ u-boot,dm-pre-reloc;
+ /* Field: vco0.psrc */
+ vco0-psrc = <0>;
+ /* Field: vco1.denom */
+ vco1-denom = <1>;
+ /* Field: vco1.numer */
+ vco1-numer = <159>;
+ /* Field: cntr2clk.cnt */
+ cntr2clk-cnt = <7>;
+ /* Field: cntr2clk.src */
+ cntr2clk-src = <1>;
+ /* Field: cntr3clk.cnt */
+ cntr3clk-cnt = <900>;
+ /* Field: cntr3clk.src */
+ cntr3clk-src = <1>;
+ /* Field: cntr4clk.cnt */
+ cntr4clk-cnt = <19>;
+ /* Field: cntr4clk.src */
+ cntr4clk-src = <1>;
+ /* Field: cntr5clk.cnt */
+ cntr5clk-cnt = <499>;
+ /* Field: cntr5clk.src */
+ cntr5clk-src = <1>;
+ /* Field: cntr6clk.cnt */
+ cntr6clk-cnt = <900>;
+ /* Field: cntr6clk.src */
+ cntr6clk-src = <1>;
+ /* Field: cntr7clk.cnt */
+ cntr7clk-cnt = <900>;
+ /* Field: cntr8clk.cnt */
+ cntr8clk-cnt = <900>;
+ /* Field: cntr8clk.src */
+ cntr8clk-src = <0>;
+ /* Field: cntr9clk.cnt */
+ cntr9clk-cnt = <900>;
+ /* Field: emacctl.emac0sel */
+ emacctl-emac0sel = <0>;
+ /* Field: emacctl.emac1sel */
+ emacctl-emac1sel = <0>;
+ /* Field: emacctl.emac2sel */
+ emacctl-emac2sel = <0>;
+ /* Field: gpiodiv.gpiodbclk */
+ gpiodiv-gpiodbclk = <32000>;
+ };
+
+ /*
+ * Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_alteragrp
+ */
+ alteragrp {
+ u-boot,dm-pre-reloc;
+ /* Register: nocclk */
+ nocclk = <0x0384000b>;
+ /* Register: mpuclk */
+ mpuclk = <0x03840001>;
+ };
+ };
+
+ /*
+ * Driver: altera_arria10_soc_3v_io48_pin_mux_arria10_uboot_driver
+ * Version: 1.0
+ * Binding: pinmux
+ */
+ i_io48_pin_mux: pinmux@0xffd07000 {
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "pinctrl-single";
+ reg = <0xffd07000 0x00000800>;
+ reg-names = "soc_3v_io48_pin_mux_OCP_SLV";
+
+ /*
+ * Address Block:
+ * soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_shared_3v_io_grp
+ */
+ shared {
+ u-boot,dm-pre-reloc;
+ reg = <0xffd07000 0x00000200>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000000f>;
+ pinctrl-single,pins =
+ /* Register: pinmux_shared_io_q1_1 */
+ <0x00000000 0x00000008>,
+ /* Register: pinmux_shared_io_q1_2 */
+ <0x00000004 0x00000008>,
+ /* Register: pinmux_shared_io_q1_3 */
+ <0x00000008 0x00000008>,
+ /* Register: pinmux_shared_io_q1_4 */
+ <0x0000000c 0x00000008>,
+ /* Register: pinmux_shared_io_q1_5 */
+ <0x00000010 0x00000008>,
+ /* Register: pinmux_shared_io_q1_6 */
+ <0x00000014 0x00000008>,
+ /* Register: pinmux_shared_io_q1_7 */
+ <0x00000018 0x00000008>,
+ /* Register: pinmux_shared_io_q1_8 */
+ <0x0000001c 0x00000008>,
+ /* Register: pinmux_shared_io_q1_9 */
+ <0x00000020 0x00000008>,
+ /* Register: pinmux_shared_io_q1_10 */
+ <0x00000024 0x00000008>,
+ /* Register: pinmux_shared_io_q1_11 */
+ <0x00000028 0x00000008>,
+ /* Register: pinmux_shared_io_q1_12 */
+ <0x0000002c 0x00000008>,
+ /* Register: pinmux_shared_io_q2_1 */
+ <0x00000030 0x00000004>,
+ /* Register: pinmux_shared_io_q2_2 */
+ <0x00000034 0x00000004>,
+ /* Register: pinmux_shared_io_q2_3 */
+ <0x00000038 0x00000004>,
+ /* Register: pinmux_shared_io_q2_4 */
+ <0x0000003c 0x00000004>,
+ /* Register: pinmux_shared_io_q2_5 */
+ <0x00000040 0x00000004>,
+ /* Register: pinmux_shared_io_q2_6 */
+ <0x00000044 0x00000004>,
+ /* Register: pinmux_shared_io_q2_7 */
+ <0x00000048 0x00000004>,
+ /* Register: pinmux_shared_io_q2_8 */
+ <0x0000004c 0x00000004>,
+ /* Register: pinmux_shared_io_q2_9 */
+ <0x00000050 0x00000004>,
+ /* Register: pinmux_shared_io_q2_10 */
+ <0x00000054 0x00000004>,
+ /* Register: pinmux_shared_io_q2_11 */
+ <0x00000058 0x00000004>,
+ /* Register: pinmux_shared_io_q2_12 */
+ <0x0000005c 0x00000004>,
+ /* Register: pinmux_shared_io_q3_1 */
+ <0x00000060 0x00000003>,
+ /* Register: pinmux_shared_io_q3_2 */
+ <0x00000064 0x00000003>,
+ /* Register: pinmux_shared_io_q3_3 */
+ <0x00000068 0x00000003>,
+ /* Register: pinmux_shared_io_q3_4 */
+ <0x0000006c 0x00000003>,
+ /* Register: pinmux_shared_io_q3_5 */
+ <0x00000070 0x00000003>,
+ /* Register: pinmux_shared_io_q3_6 */
+ <0x00000074 0x0000000f>,
+ /* Register: pinmux_shared_io_q3_7 */
+ <0x00000078 0x0000000a>,
+ /* Register: pinmux_shared_io_q3_8 */
+ <0x0000007c 0x0000000a>,
+ /* Register: pinmux_shared_io_q3_9 */
+ <0x00000080 0x0000000a>,
+ /* Register: pinmux_shared_io_q3_10 */
+ <0x00000084 0x0000000a>,
+ /* Register: pinmux_shared_io_q3_11 */
+ <0x00000088 0x00000001>,
+ /* Register: pinmux_shared_io_q3_12 */
+ <0x0000008c 0x00000001>,
+ /* Register: pinmux_shared_io_q4_1 */
+ <0x00000090 0x00000000>,
+ /* Register: pinmux_shared_io_q4_2 */
+ <0x00000094 0x00000000>,
+ /* Register: pinmux_shared_io_q4_3 */
+ <0x00000098 0x0000000f>,
+ /* Register: pinmux_shared_io_q4_4 */
+ <0x0000009c 0x0000000c>,
+ /* Register: pinmux_shared_io_q4_5 */
+ <0x000000a0 0x0000000f>,
+ /* Register: pinmux_shared_io_q4_6 */
+ <0x000000a4 0x0000000f>,
+ /* Register: pinmux_shared_io_q4_7 */
+ <0x000000a8 0x0000000a>,
+ /* Register: pinmux_shared_io_q4_8 */
+ <0x000000ac 0x0000000a>,
+ /* Register: pinmux_shared_io_q4_9 */
+ <0x000000b0 0x0000000c>,
+ /* Register: pinmux_shared_io_q4_10 */
+ <0x000000b4 0x0000000c>,
+ /* Register: pinmux_shared_io_q4_11 */
+ <0x000000b8 0x0000000c>,
+ /* Register: pinmux_shared_io_q4_12 */
+ <0x000000bc 0x0000000c>;
+ };
+
+ /*
+ * Address Block:
+ * soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp
+ */
+ dedicated {
+ u-boot,dm-pre-reloc;
+ reg = <0xffd07200 0x00000200>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000000f>;
+ pinctrl-single,pins =
+ /* Register: pinmux_dedicated_io_4 */
+ <0x0000000c 0x00000004>,
+ /* Register: pinmux_dedicated_io_5 */
+ <0x00000010 0x00000004>,
+ /* Register: pinmux_dedicated_io_6 */
+ <0x00000014 0x00000004>,
+ /* Register: pinmux_dedicated_io_7 */
+ <0x00000018 0x00000004>,
+ /* Register: pinmux_dedicated_io_8 */
+ <0x0000001c 0x00000004>,
+ /* Register: pinmux_dedicated_io_9 */
+ <0x00000020 0x00000004>,
+ /* Register: pinmux_dedicated_io_10 */
+ <0x00000024 0x0000000a>,
+ /* Register: pinmux_dedicated_io_11 */
+ <0x00000028 0x0000000a>,
+ /* Register: pinmux_dedicated_io_12 */
+ <0x0000002c 0x0000000a>,
+ /* Register: pinmux_dedicated_io_13 */
+ <0x00000030 0x0000000a>,
+ /* Register: pinmux_dedicated_io_14 */
+ <0x00000034 0x0000000a>,
+ /* Register: pinmux_dedicated_io_15 */
+ <0x00000038 0x0000000a>,
+ /* Register: pinmux_dedicated_io_16 */
+ <0x0000003c 0x0000000d>,
+ /* Register: pinmux_dedicated_io_17 */
+ <0x00000040 0x0000000d>;
+ };
+
+ /*
+ * Address Block:
+ * soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp
+ */
+ dedicated_cfg {
+ u-boot,dm-pre-reloc;
+ reg = <0xffd07200 0x00000200>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x003f3f3f>;
+ pinctrl-single,pins =
+ /* Register: configuration_dedicated_io_bank */
+ <0x00000100 0x00000101>,
+ /* Register: configuration_dedicated_io_1 */
+ <0x00000104 0x000b080a>,
+ /* Register: configuration_dedicated_io_2 */
+ <0x00000108 0x000b080a>,
+ /* Register: configuration_dedicated_io_3 */
+ <0x0000010c 0x000b080a>,
+ /* Register: configuration_dedicated_io_4 */
+ <0x00000110 0x0008282a>,
+ /* Register: configuration_dedicated_io_5 */
+ <0x00000114 0x000a282a>,
+ /* Register: configuration_dedicated_io_6 */
+ <0x00000118 0x0008282a>,
+ /* Register: configuration_dedicated_io_7 */
+ <0x0000011c 0x000a282a>,
+ /* Register: configuration_dedicated_io_8 */
+ <0x00000120 0x000a282a>,
+ /* Register: configuration_dedicated_io_9 */
+ <0x00000124 0x000a282a>,
+ /* Register: configuration_dedicated_io_10 */
+ <0x00000128 0x00090000>,
+ /* Register: configuration_dedicated_io_11 */
+ <0x0000012c 0x00090000>,
+ /* Register: configuration_dedicated_io_12 */
+ <0x00000130 0x00090000>,
+ /* Register: configuration_dedicated_io_13 */
+ <0x00000134 0x00090000>,
+ /* Register: configuration_dedicated_io_14 */
+ <0x00000138 0x00090000>,
+ /* Register: configuration_dedicated_io_15 */
+ <0x0000013c 0x00090000>,
+ /* Register: configuration_dedicated_io_16 */
+ <0x00000140 0x0008282a>,
+ /* Register: configuration_dedicated_io_17 */
+ <0x00000144 0x000a282a>;
+ };
+
+ /*
+ * Address Block:
+ * soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_fpga_interface_grp
+ */
+ fpga {
+ u-boot,dm-pre-reloc;
+ reg = <0xffd07400 0x00000100>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x00000001>;
+ pinctrl-single,pins =
+ /* Register: pinmux_emac0_usefpga */
+ <0x00000000 0x00000000>,
+ /* Register: pinmux_emac1_usefpga */
+ <0x00000004 0x00000000>,
+ /* Register: pinmux_emac2_usefpga */
+ <0x00000008 0x00000000>,
+ /* Register: pinmux_i2c0_usefpga */
+ <0x0000000c 0x00000000>,
+ /* Register: pinmux_i2c1_usefpga */
+ <0x00000010 0x00000000>,
+ /* Register: pinmux_i2c_emac0_usefpga */
+ <0x00000014 0x00000000>,
+ /* Register: pinmux_i2c_emac1_usefpga */
+ <0x00000018 0x00000000>,
+ /* Register: pinmux_i2c_emac2_usefpga */
+ <0x0000001c 0x00000000>,
+ /* Register: pinmux_nand_usefpga */
+ <0x00000020 0x00000000>,
+ /* Register: pinmux_qspi_usefpga */
+ <0x00000024 0x00000000>,
+ /* Register: pinmux_sdmmc_usefpga */
+ <0x00000028 0x00000000>,
+ /* Register: pinmux_spim0_usefpga */
+ <0x0000002c 0x00000000>,
+ /* Register: pinmux_spim1_usefpga */
+ <0x00000030 0x00000000>,
+ /* Register: pinmux_spis0_usefpga */
+ <0x00000034 0x00000000>,
+ /* Register: pinmux_spis1_usefpga */
+ <0x00000038 0x00000000>,
+ /* Register: pinmux_uart0_usefpga */
+ <0x0000003c 0x00000000>,
+ /* Register: pinmux_uart1_usefpga */
+ <0x00000040 0x00000000>;
+ };
+ };
+
+ /*
+ * Driver: altera_arria10_soc_noc_arria10_uboot_driver
+ * Version: 1.0
+ * Binding: device
+ */
+ i_noc: noc@0xffd10000 {
+ u-boot,dm-pre-reloc;
+ compatible = "altr,socfpga-a10-noc";
+ reg = <0xffd10000 0x00008000>;
+ reg-names = "mpu_m0";
+
+ firewall {
+ u-boot,dm-pre-reloc;
+ /*
+ * Driver setting:
+ * altera_arria10_soc_noc_arria10_uboot_driver.
+ * I_NOC.mpu_m0.
+ * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.base
+ *
+ * Driver setting:
+ * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.
+ * mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
+ * mpuregion0addr.limit
+ */
+ mpu0 = <0x00000000 0x0000ffff>;
+ /*
+ * Driver setting:
+ * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.
+ * mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.base
+ *
+ * Driver setting:
+ * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.
+ * mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.limit
+ */
+ l3-0 = <0x00000000 0x0000ffff>;
+ /*
+ * Driver setting:
+ * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.
+ * mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
+ * fpga2sdram0region0addr.base
+ *
+ * Driver setting:
+ * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.
+ * mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
+ * fpga2sdram0region0addr.limit
+ */
+ fpga2sdram0-0 = <0x00000000 0x0000ffff>;
+ /*
+ * Driver setting:
+ * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.
+ * mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
+ * fpga2sdram1region0addr.base
+ *
+ * Driver setting:
+ * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.
+ * mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
+ * fpga2sdram1region0addr.limit
+ */
+ fpga2sdram1-0 = <0x00000000 0x0000ffff>;
+ /*
+ * Driver setting:
+ * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.
+ * mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
+ * fpga2sdram2region0addr.base
+ *
+ * Driver setting:
+ * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.
+ * mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
+ * fpga2sdram2region0addr.limit
+ */
+ fpga2sdram2-0 = <0x00000000 0x0000ffff>;
+ };
+ };
+
+ hps_fpgabridge0: fpgabridge@0 {
+ compatible = "altr,socfpga-hps2fpga-bridge";
+ init-val = <1>;
+ };
+
+ hps_fpgabridge1: fpgabridge@1 {
+ compatible = "altr,socfpga-lwhps2fpga-bridge";
+ init-val = <1>;
+ };
+
+ hps_fpgabridge2: fpgabridge@2 {
+ compatible = "altr,socfpga-fpga2hps-bridge";
+ init-val = <1>;
+ };
+
+ hps_fpgabridge3: fpgabridge@3 {
+ compatible = "altr,socfpga-fpga2sdram0-bridge";
+ init-val = <1>;
+ };
+
+ hps_fpgabridge4: fpgabridge@4 {
+ compatible = "altr,socfpga-fpga2sdram1-bridge";
+ init-val = <0>;
+ };
+
+ hps_fpgabridge5: fpgabridge@5 {
+ compatible = "altr,socfpga-fpga2sdram2-bridge";
+ init-val = <1>;
+ };
+};
--
2.13.0
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