From: Xiaowei Bao <xiaowei....@nxp.com> The VF_BARn_REG register's Prefetchable and Type bit fields are overwritten by a write to VF's BAR Mask register. workaround: Before writing to the VF_BARn_MASK_REG register, write 0b to the PCIE_MISC_CONTROL_1_OFF register.
Signed-off-by: Xiaowei Bao <xiaowei....@nxp.com> --- v2: - Add the NXP copyright. drivers/pci/pcie_layerscape.c | 9 +++++++++ drivers/pci/pcie_layerscape.h | 1 + 2 files changed, 10 insertions(+), 0 deletions(-) diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index 8f5ebda..25c5a0c 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -446,6 +446,15 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie) if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) { pcie->sriov_flag = 1; for (pf = 0; pf < PCIE_PF_NUM; pf++) { + /* + * The VF_BARn_REG register's Prefetchable and Type bit + * fields are overwritten by a write to VF's BAR Mask + * register. Before writing to the VF_BARn_MASK_REG + * register, write 0b to the PCIE_MISC_CONTROL_1_OFF + * register. + */ + writel(0, pcie->dbi + PCIE_MISC_CONTROL_1_OFF); + if (pcie->cfg2_flag) { for (vf = 0; vf <= PCIE_VF_NUM; vf++) { ctrl_writel(pcie, diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index eb910ba..c6f1cb2 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -94,6 +94,7 @@ #define PCIE_BAR4_SIZE SZ_1M /* 1M */ #define PCIE_SRIOV_VFBAR0 0x19C +#define PCIE_MISC_CONTROL_1_OFF 0x8BC #define PCIE_CTRL1_FUNC_NUM(pf) (pf << 20) #define PCIE_MASK_OFFSET(flag, pf) ((flag) ? 0 : (0x1000 + 0x20000 * (pf))) -- 1.7.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot