This fix issue when access config from PCIe switch.
The PCIe controller need to send Type 0 config TLP if the targeting bus
matches with the secondary bus number, which is when the TLP is targeting
the immediate device on the link.
The PCIe controller send Type 1 config TLP if the targeting bus is
larger than the secondary bus, which is when the TLP is targeting the
device not immediate on the link.
Signed-off-by: Ley Foon Tan <ley.foon....@intel.com>
---
drivers/pci/pcie_intel_fpga.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c
index a096d1c697..a5ea4888f3 100644
--- a/drivers/pci/pcie_intel_fpga.c
+++ b/drivers/pci/pcie_intel_fpga.c
@@ -36,16 +36,18 @@
#define RP_CFG_ADDR(pcie, reg) \
((pcie->hip_base) + (reg) + (1 << 20))
+#define RP_SECONDARY(pcie) \
+ readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
#define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
#define TLP_CFGRD_DW0(pcie, bus) \
- ((((bus != pcie->first_busno) ? TLP_FMTTYPE_CFGRD0 \
- : TLP_FMTTYPE_CFGRD1) << 24) | \
+ ((((bus > RP_SECONDARY(pcie)) ? TLP_FMTTYPE_CFGRD1 \
+ : TLP_FMTTYPE_CFGRD0) << 24) | \
TLP_PAYLOAD_SIZE)
#define TLP_CFGWR_DW0(pcie, bus) \
- ((((bus != pcie->first_busno) ? TLP_FMTTYPE_CFGWR0 \
- : TLP_FMTTYPE_CFGWR1) << 24) | \
+ ((((bus > RP_SECONDARY(pcie)) ? TLP_FMTTYPE_CFGWR1 \
+ : TLP_FMTTYPE_CFGWR0) << 24) | \
TLP_PAYLOAD_SIZE)
#define TLP_CFG_DW1(pcie, tag, be) \
--
2.19.0
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