On 06/06/19 7:24 PM, Faiz Abbas wrote:
> The HOST_CONTROL2 register is a part of SDHC v3.00 and not just specific
> to arasan/zynq controllers. Add the same to sdhci.h.
>
> Also create a common API to set UHS timings in HOST_CONTROL2.
>
> Signed-off-by: Faiz Abbas <faiz_ab...@ti.com>
> Reviewed-by: Tom Rini <tr...@konsulko.com>
> Tested-by: Lokesh Vutla <lokeshvu...@ti.com>
This is causing build failure for the following defconfig:
xilinx_zynqmp_zcu104_revA_defconfig
➜ u-boot git:(master) v78make xilinx_zynqmp_zcu104_revA_defconfig
HOSTCC scripts/basic/fixdep
HOSTCC scripts/kconfig/conf.o
YACC scripts/kconfig/zconf.tab.c
LEX scripts/kconfig/zconf.lex.c
HOSTCC scripts/kconfig/zconf.tab.o
v8 HOSTLD scripts/kconfig/conf
#
# configuration written to .config
#
➜ u-boot git:(master) v78make -j4 -s
drivers/mmc/zynq_sdhci.c: In function ‘arasan_sdhci_execute_tuning’:
drivers/mmc/zynq_sdhci.c:97:27: error: ‘SDHCI_HOST_CTRL2’ undeclared (first use
in this function); did you mean ‘SDHCI_HOST_CONTROL2’?
ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);
^~~~~~~~~~~~~~~~
SDHCI_HOST_CONTROL2
drivers/mmc/zynq_sdhci.c:97:27: note: each undeclared identifier is reported
only once for each function it appears in
drivers/mmc/zynq_sdhci.c: In function ‘arasan_sdhci_set_control_reg’:
drivers/mmc/zynq_sdhci.c:182:27: error: ‘SDHCI_HOST_CTRL2’ undeclared (first use
in this function); did you mean ‘SDHCI_HOST_CONTROL2’?
reg = sdhci_readw(host, SDHCI_HOST_CTRL2);
^~~~~~~~~~~~~~~~
SDHCI_HOST_CONTROL2
drivers/mmc/zynq_sdhci.c:183:10: error: ‘SDHCI_18V_SIGNAL’ undeclared (first use
in this function); did you mean ‘SDHCI_DIV_HI_MASK’?
reg |= SDHCI_18V_SIGNAL;
^~~~~~~~~~~~~~~~
SDHCI_DIV_HI_MASK
scripts/Makefile.build:278: recipe for target 'drivers/mmc/zynq_sdhci.o' failed
make[2]: *** [drivers/mmc/zynq_sdhci.o] Error 1
scripts/Makefile.build:432: recipe for target 'drivers/mmc' failed
make[1]: *** [drivers/mmc] Error 2
Makefile:1582: recipe for target 'drivers' failed
make: *** [drivers] Error 2
make: *** Waiting for unfinished jobs....
Can you fix it and repost the series?
Thanks and regards,
Lokesh
> ---
> drivers/mmc/sdhci.c | 28 ++++++++++++++++++++++++++++
> drivers/mmc/zynq_sdhci.c | 31 ++-----------------------------
> include/sdhci.h | 19 ++++++++++++++++++-
> 3 files changed, 48 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
> index 75e6567631..79edb18fe5 100644
> --- a/drivers/mmc/sdhci.c
> +++ b/drivers/mmc/sdhci.c
> @@ -533,6 +533,34 @@ static void sdhci_set_power(struct sdhci_host *host,
> unsigned short power)
> sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
> }
>
> +void sdhci_set_uhs_timing(struct sdhci_host *host)
> +{
> + struct mmc *mmc = (struct mmc *)host->mmc;
> + u32 reg;
> +
> + reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
> + reg &= ~SDHCI_CTRL_UHS_MASK;
> +
> + switch (mmc->selected_mode) {
> + case UHS_SDR50:
> + case MMC_HS_52:
> + reg |= SDHCI_CTRL_UHS_SDR50;
> + break;
> + case UHS_DDR50:
> + case MMC_DDR_52:
> + reg |= SDHCI_CTRL_UHS_DDR50;
> + break;
> + case UHS_SDR104:
> + case MMC_HS_200:
> + reg |= SDHCI_CTRL_UHS_SDR104;
> + break;
> + default:
> + reg |= SDHCI_CTRL_UHS_SDR12;
> + }
> +
> + sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
> +}
> +
> #ifdef CONFIG_DM_MMC
> static int sdhci_set_ios(struct udevice *dev)
> {
> diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
> index 08023783de..b39e1d7a19 100644
> --- a/drivers/mmc/zynq_sdhci.c
> +++ b/drivers/mmc/zynq_sdhci.c
> @@ -48,11 +48,6 @@ static const u8 mode2timing[] = {
> [MMC_HS_200] = MMC_HS200_BUS_SPEED,
> };
>
> -#define SDHCI_HOST_CTRL2 0x3E
> -#define SDHCI_CTRL2_MODE_MASK 0x7
> -#define SDHCI_18V_SIGNAL 0x8
> -#define SDHCI_CTRL_EXEC_TUNING 0x0040
> -#define SDHCI_CTRL_TUNED_CLK 0x80
> #define SDHCI_TUNING_LOOP_COUNT 40
>
> static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid)
> @@ -190,30 +185,8 @@ static void arasan_sdhci_set_control_reg(struct
> sdhci_host *host)
> }
>
> if (mmc->selected_mode > SD_HS &&
> - mmc->selected_mode <= UHS_DDR50) {
> - reg = sdhci_readw(host, SDHCI_HOST_CTRL2);
> - reg &= ~SDHCI_CTRL2_MODE_MASK;
> - switch (mmc->selected_mode) {
> - case UHS_SDR12:
> - reg |= UHS_SDR12_BUS_SPEED;
> - break;
> - case UHS_SDR25:
> - reg |= UHS_SDR25_BUS_SPEED;
> - break;
> - case UHS_SDR50:
> - reg |= UHS_SDR50_BUS_SPEED;
> - break;
> - case UHS_SDR104:
> - reg |= UHS_SDR104_BUS_SPEED;
> - break;
> - case UHS_DDR50:
> - reg |= UHS_DDR50_BUS_SPEED;
> - break;
> - default:
> - break;
> - }
> - sdhci_writew(host, reg, SDHCI_HOST_CTRL2);
> - }
> + mmc->selected_mode <= UHS_DDR50)
> + sdhci_set_uhs_timing(host);
> }
> #endif
>
> diff --git a/include/sdhci.h b/include/sdhci.h
> index 3dcbc14965..01addb7a60 100644
> --- a/include/sdhci.h
> +++ b/include/sdhci.h
> @@ -144,7 +144,23 @@
>
> #define SDHCI_ACMD12_ERR 0x3C
>
> -/* 3E-3F reserved */
> +#define SDHCI_HOST_CONTROL2 0x3E
> +#define SDHCI_CTRL_UHS_MASK 0x0007
> +#define SDHCI_CTRL_UHS_SDR12 0x0000
> +#define SDHCI_CTRL_UHS_SDR25 0x0001
> +#define SDHCI_CTRL_UHS_SDR50 0x0002
> +#define SDHCI_CTRL_UHS_SDR104 0x0003
> +#define SDHCI_CTRL_UHS_DDR50 0x0004
> +#define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
> +#define SDHCI_CTRL_VDD_180 0x0008
> +#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
> +#define SDHCI_CTRL_DRV_TYPE_B 0x0000
> +#define SDHCI_CTRL_DRV_TYPE_A 0x0010
> +#define SDHCI_CTRL_DRV_TYPE_C 0x0020
> +#define SDHCI_CTRL_DRV_TYPE_D 0x0030
> +#define SDHCI_CTRL_EXEC_TUNING 0x0040
> +#define SDHCI_CTRL_TUNED_CLK 0x0080
> +#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
>
> #define SDHCI_CAPABILITIES 0x40
> #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
> @@ -467,6 +483,7 @@ int sdhci_bind(struct udevice *dev, struct mmc *mmc,
> struct mmc_config *cfg);
> int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min);
> #endif /* !CONFIG_BLK */
>
> +void sdhci_set_uhs_timing(struct sdhci_host *host);
> #ifdef CONFIG_DM_MMC
> /* Export the operations to drivers */
> int sdhci_probe(struct udevice *dev);
>
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