Hi Heiko, On Fri, Jun 7, 2019 at 10:58 AM Heiko Schocher <h...@denx.de> wrote: > > Hello Mario, > > Am 07.06.2019 um 09:51 schrieb Mario Six: > > This commit does the minimal possible conversion so that the ids8313 > > board still compiles with the recent SPI DM conversion: > > * Add a device tree (for now a 1-to-1 copy of the mpc8313erdb board's DT > > from the Linux kernel sources) > > * Remove the legacy CS switching mechanism from the board file > > * Enable enough config options to that the board compiles > > > > Signed-off-by: Mario Six <mario....@gdsys.cc> > > --- > > arch/powerpc/dts/Makefile | 1 + > > arch/powerpc/dts/ids8313.dts | 405 +++++++++++++++++++++++++++++++++++ > > board/ids/ids8313/ids8313.c | 32 --- > > configs/ids8313_defconfig | 6 +- > > 4 files changed, 411 insertions(+), 33 deletions(-) > > create mode 100644 arch/powerpc/dts/ids8313.dts > > Thanks for putting effort here ... > > I try to get infos if we can drop this board from mainline... > > As the board blocks spi patches ... can we remove SPI from this board > completly instead adding (simple copy) a dts which does not fit for > the board? > Indeed, if the perspective of removal is there, then disabling SPI is easier.
Consider the patch obsolete, then. :-) > Thanks! > > bye, > Heiko Best regards, Mario > > diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile > > index 6a28f802c2..f43f46870c 100644 > > --- a/arch/powerpc/dts/Makefile > > +++ b/arch/powerpc/dts/Makefile > > @@ -3,6 +3,7 @@ > > dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb > > dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb > > dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb > > +dtb-$(CONFIG_TARGET_IDS8313) += ids8313.dtb > > > > targets += $(dtb-y) > > > > diff --git a/arch/powerpc/dts/ids8313.dts b/arch/powerpc/dts/ids8313.dts > > new file mode 100644 > > index 0000000000..a8315795b2 > > --- /dev/null > > +++ b/arch/powerpc/dts/ids8313.dts > > @@ -0,0 +1,405 @@ > > +// SPDX-License-Identifier: GPL-2.0-or-later > > +/* > > + * MPC8313E RDB Device Tree Source > > + * > > + * Copyright 2005, 2006, 2007 Freescale Semiconductor Inc. > > + */ > > + > > +/dts-v1/; > > + > > +/ { > > + model = "MPC8313ERDB"; > > + compatible = "MPC8313ERDB", "MPC831xRDB", "MPC83xxRDB"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + aliases { > > + ethernet0 = &enet0; > > + ethernet1 = &enet1; > > + serial0 = &serial0; > > + serial1 = &serial1; > > + pci0 = &pci0; > > + }; > > + > > + cpus { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + PowerPC,8313@0 { > > + device_type = "cpu"; > > + reg = <0x0>; > > + d-cache-line-size = <32>; > > + i-cache-line-size = <32>; > > + d-cache-size = <16384>; > > + i-cache-size = <16384>; > > + timebase-frequency = <0>; // from bootloader > > + bus-frequency = <0>; // from bootloader > > + clock-frequency = <0>; // from bootloader > > + }; > > + }; > > + > > + memory { > > + device_type = "memory"; > > + reg = <0x00000000 0x08000000>; // 128MB at 0 > > + }; > > + > > + localbus@e0005000 { > > + #address-cells = <2>; > > + #size-cells = <1>; > > + compatible = "fsl,mpc8313-elbc", "fsl,elbc", "simple-bus"; > > + reg = <0xe0005000 0x1000>; > > + interrupts = <77 0x8>; > > + interrupt-parent = <&ipic>; > > + > > + // CS0 and CS1 are swapped when > > + // booting from nand, but the > > + // addresses are the same. > > + ranges = <0x0 0x0 0xfe000000 0x00800000 > > + 0x1 0x0 0xe2800000 0x00008000 > > + 0x2 0x0 0xf0000000 0x00020000 > > + 0x3 0x0 0xfa000000 0x00008000>; > > + > > + flash@0,0 { > > + #address-cells = <1>; > > + #size-cells = <1>; > > + compatible = "cfi-flash"; > > + reg = <0x0 0x0 0x800000>; > > + bank-width = <2>; > > + device-width = <1>; > > + }; > > + > > + nand@1,0 { > > + #address-cells = <1>; > > + #size-cells = <1>; > > + compatible = "fsl,mpc8313-fcm-nand", > > + "fsl,elbc-fcm-nand"; > > + reg = <0x1 0x0 0x2000>; > > + > > + u-boot@0 { > > + reg = <0x0 0x100000>; > > + read-only; > > + }; > > + > > + kernel@100000 { > > + reg = <0x100000 0x300000>; > > + }; > > + > > + fs@400000 { > > + reg = <0x400000 0x1c00000>; > > + }; > > + }; > > + }; > > + > > + soc8313@e0000000 { > > + #address-cells = <1>; > > + #size-cells = <1>; > > + device_type = "soc"; > > + compatible = "simple-bus"; > > + ranges = <0x0 0xe0000000 0x00100000>; > > + reg = <0xe0000000 0x00000200>; > > + bus-frequency = <0>; > > + > > + wdt@200 { > > + device_type = "watchdog"; > > + compatible = "mpc83xx_wdt"; > > + reg = <0x200 0x100>; > > + }; > > + > > + sleep-nexus { > > + #address-cells = <1>; > > + #size-cells = <1>; > > + compatible = "simple-bus"; > > + sleep = <&pmc 0x03000000>; > > + ranges; > > + > > + i2c@3000 { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + cell-index = <0>; > > + compatible = "fsl-i2c"; > > + reg = <0x3000 0x100>; > > + interrupts = <14 0x8>; > > + interrupt-parent = <&ipic>; > > + dfsrr; > > + rtc@68 { > > + compatible = "dallas,ds1339"; > > + reg = <0x68>; > > + }; > > + }; > > + > > + crypto@30000 { > > + compatible = "fsl,sec2.2", "fsl,sec2.1", > > + "fsl,sec2.0"; > > + reg = <0x30000 0x10000>; > > + interrupts = <11 0x8>; > > + interrupt-parent = <&ipic>; > > + fsl,num-channels = <1>; > > + fsl,channel-fifo-len = <24>; > > + fsl,exec-units-mask = <0x4c>; > > + fsl,descriptor-types-mask = <0x0122003f>; > > + }; > > + }; > > + > > + i2c@3100 { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + cell-index = <1>; > > + compatible = "fsl-i2c"; > > + reg = <0x3100 0x100>; > > + interrupts = <15 0x8>; > > + interrupt-parent = <&ipic>; > > + dfsrr; > > + }; > > + > > + spi@7000 { > > + cell-index = <0>; > > + compatible = "fsl,spi"; > > + reg = <0x7000 0x1000>; > > + interrupts = <16 0x8>; > > + interrupt-parent = <&ipic>; > > + mode = "cpu"; > > + }; > > + > > + /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ > > + usb@23000 { > > + compatible = "fsl-usb2-dr"; > > + reg = <0x23000 0x1000>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + interrupt-parent = <&ipic>; > > + interrupts = <38 0x8>; > > + phy_type = "utmi_wide"; > > + sleep = <&pmc 0x00300000>; > > + }; > > + > > + ptp_clock@24E00 { > > + compatible = "fsl,etsec-ptp"; > > + reg = <0x24E00 0xB0>; > > + interrupts = <12 0x8 13 0x8>; > > + interrupt-parent = < &ipic >; > > + fsl,tclk-period = <10>; > > + fsl,tmr-prsc = <100>; > > + fsl,tmr-add = <0x999999A4>; > > + fsl,tmr-fiper1 = <0x3B9AC9F6>; > > + fsl,tmr-fiper2 = <0x00018696>; > > + fsl,max-adj = <659999998>; > > + }; > > + > > + enet0: ethernet@24000 { > > + #address-cells = <1>; > > + #size-cells = <1>; > > + sleep = <&pmc 0x20000000>; > > + ranges = <0x0 0x24000 0x1000>; > > + > > + cell-index = <0>; > > + device_type = "network"; > > + model = "eTSEC"; > > + compatible = "gianfar"; > > + reg = <0x24000 0x1000>; > > + local-mac-address = [ 00 00 00 00 00 00 ]; > > + interrupts = <37 0x8 36 0x8 35 0x8>; > > + interrupt-parent = <&ipic>; > > + tbi-handle = < &tbi0 >; > > + /* Vitesse 7385 isn't on the MDIO bus */ > > + fixed-link = <1 1 1000 0 0>; > > + fsl,magic-packet; > > + > > + mdio@520 { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + compatible = "fsl,gianfar-mdio"; > > + reg = <0x520 0x20>; > > + phy4: ethernet-phy@4 { > > + interrupt-parent = <&ipic>; > > + interrupts = <20 0x8>; > > + reg = <0x4>; > > + }; > > + tbi0: tbi-phy@11 { > > + reg = <0x11>; > > + device_type = "tbi-phy"; > > + }; > > + }; > > + }; > > + > > + enet1: ethernet@25000 { > > + #address-cells = <1>; > > + #size-cells = <1>; > > + cell-index = <1>; > > + device_type = "network"; > > + model = "eTSEC"; > > + compatible = "gianfar"; > > + reg = <0x25000 0x1000>; > > + ranges = <0x0 0x25000 0x1000>; > > + local-mac-address = [ 00 00 00 00 00 00 ]; > > + interrupts = <34 0x8 33 0x8 32 0x8>; > > + interrupt-parent = <&ipic>; > > + tbi-handle = < &tbi1 >; > > + phy-handle = < &phy4 >; > > + sleep = <&pmc 0x10000000>; > > + fsl,magic-packet; > > + > > + mdio@520 { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + compatible = "fsl,gianfar-tbi"; > > + reg = <0x520 0x20>; > > + > > + tbi1: tbi-phy@11 { > > + reg = <0x11>; > > + device_type = "tbi-phy"; > > + }; > > + }; > > + > > + > > + }; > > + > > + serial0: serial@4500 { > > + cell-index = <0>; > > + device_type = "serial"; > > + compatible = "fsl,ns16550", "ns16550"; > > + reg = <0x4500 0x100>; > > + clock-frequency = <0>; > > + interrupts = <9 0x8>; > > + interrupt-parent = <&ipic>; > > + }; > > + > > + serial1: serial@4600 { > > + cell-index = <1>; > > + device_type = "serial"; > > + compatible = "fsl,ns16550", "ns16550"; > > + reg = <0x4600 0x100>; > > + clock-frequency = <0>; > > + interrupts = <10 0x8>; > > + interrupt-parent = <&ipic>; > > + }; > > + > > + /* IPIC > > + * interrupts cell = <intr #, sense> > > + * sense values match linux IORESOURCE_IRQ_* defines: > > + * sense == 8: Level, low assertion > > + * sense == 2: Edge, high-to-low change > > + */ > > + ipic: pic@700 { > > + interrupt-controller; > > + #address-cells = <0>; > > + #interrupt-cells = <2>; > > + reg = <0x700 0x100>; > > + device_type = "ipic"; > > + }; > > + > > + pmc: power@b00 { > > + compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc"; > > + reg = <0xb00 0x100 0xa00 0x100>; > > + interrupts = <80 8>; > > + interrupt-parent = <&ipic>; > > + fsl,mpc8313-wakeup-timer = <>m1>; > > + > > + /* Remove this (or change to "okay") if you have > > + * a REVA3 or later board, if you apply one of the > > + * workarounds listed in section 8.5 of the board > > + * manual, or if you are adapting this device tree > > + * to a different board. > > + */ > > + status = "fail"; > > + }; > > + > > + gtm1: timer@500 { > > + compatible = "fsl,mpc8313-gtm", "fsl,gtm"; > > + reg = <0x500 0x100>; > > + interrupts = <90 8 78 8 84 8 72 8>; > > + interrupt-parent = <&ipic>; > > + }; > > + > > + timer@600 { > > + compatible = "fsl,mpc8313-gtm", "fsl,gtm"; > > + reg = <0x600 0x100>; > > + interrupts = <91 8 79 8 85 8 73 8>; > > + interrupt-parent = <&ipic>; > > + }; > > + }; > > + > > + sleep-nexus { > > + #address-cells = <1>; > > + #size-cells = <1>; > > + compatible = "simple-bus"; > > + sleep = <&pmc 0x00010000>; > > + ranges; > > + > > + pci0: pci@e0008500 { > > + cell-index = <1>; > > + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; > > + interrupt-map = < > > + /* IDSEL 0x0E -mini PCI */ > > + 0x7000 0x0 0x0 0x1 &ipic 18 0x8 > > + 0x7000 0x0 0x0 0x2 &ipic 18 0x8 > > + 0x7000 0x0 0x0 0x3 &ipic 18 0x8 > > + 0x7000 0x0 0x0 0x4 &ipic 18 0x8 > > + > > + /* IDSEL 0x0F - PCI slot */ > > + 0x7800 0x0 0x0 0x1 &ipic 17 0x8 > > + 0x7800 0x0 0x0 0x2 &ipic 18 0x8 > > + 0x7800 0x0 0x0 0x3 &ipic 17 0x8 > > + 0x7800 0x0 0x0 0x4 &ipic 18 0x8>; > > + interrupt-parent = <&ipic>; > > + interrupts = <66 0x8>; > > + bus-range = <0x0 0x0>; > > + ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 > > 0x10000000 > > + 0x42000000 0x0 0x80000000 0x80000000 0x0 > > 0x10000000 > > + 0x01000000 0x0 0x00000000 0xe2000000 0x0 > > 0x00100000>; > > + clock-frequency = <66666666>; > > + #interrupt-cells = <1>; > > + #size-cells = <2>; > > + #address-cells = <3>; > > + reg = <0xe0008500 0x100 /* internal registers > > */ > > + 0xe0008300 0x8>; /* config space > > access registers */ > > + compatible = "fsl,mpc8349-pci"; > > + device_type = "pci"; > > + }; > > + > > + dma@82a8 { > > + #address-cells = <1>; > > + #size-cells = <1>; > > + compatible = "fsl,mpc8313-dma", "fsl,elo-dma"; > > + reg = <0xe00082a8 4>; > > + ranges = <0 0xe0008100 0x1a8>; > > + interrupt-parent = <&ipic>; > > + interrupts = <71 8>; > > + > > + dma-channel@0 { > > + compatible = "fsl,mpc8313-dma-channel", > > + "fsl,elo-dma-channel"; > > + reg = <0 0x28>; > > + interrupt-parent = <&ipic>; > > + interrupts = <71 8>; > > + cell-index = <0>; > > + }; > > + > > + dma-channel@80 { > > + compatible = "fsl,mpc8313-dma-channel", > > + "fsl,elo-dma-channel"; > > + reg = <0x80 0x28>; > > + interrupt-parent = <&ipic>; > > + interrupts = <71 8>; > > + cell-index = <1>; > > + }; > > + > > + dma-channel@100 { > > + compatible = "fsl,mpc8313-dma-channel", > > + "fsl,elo-dma-channel"; > > + reg = <0x100 0x28>; > > + interrupt-parent = <&ipic>; > > + interrupts = <71 8>; > > + cell-index = <2>; > > + }; > > + > > + dma-channel@180 { > > + compatible = "fsl,mpc8313-dma-channel", > > + "fsl,elo-dma-channel"; > > + reg = <0x180 0x28>; > > + interrupt-parent = <&ipic>; > > + interrupts = <71 8>; > > + cell-index = <3>; > > + }; > > + }; > > + }; > > +}; > > diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c > > index caa36064f0..630a36191d 100644 > > --- a/board/ids/ids8313/ids8313.c > > +++ b/board/ids/ids8313/ids8313.c > > @@ -177,35 +177,3 @@ int misc_init_r(void) > > return 0; > > } > > #endif > > - > > -#ifdef CONFIG_MPC8XXX_SPI > > -/* > > - * The following are used to control the SPI chip selects > > - */ > > -int spi_cs_is_valid(unsigned int bus, unsigned int cs) > > -{ > > - return bus == 0 && ((cs >= 0) && (cs <= 2)); > > -} > > - > > -void spi_cs_activate(struct spi_slave *slave) > > -{ > > - gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; > > - u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE; > > - > > - /* select the spi_cs channel */ > > - out_8(spi_base, 1 << slave->cs); > > - /* activate the spi_cs */ > > - clrbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK); > > -} > > - > > -void spi_cs_deactivate(struct spi_slave *slave) > > -{ > > - gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; > > - u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE; > > - > > - /* select the spi_cs channel */ > > - out_8(spi_base, 1 << slave->cs); > > - /* deactivate the spi_cs */ > > - setbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK); > > -} > > -#endif > > diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig > > index 43454a122b..796e93570a 100644 > > --- a/configs/ids8313_defconfig > > +++ b/configs/ids8313_defconfig > > @@ -146,8 +146,12 @@ CONFIG_CMD_MTDPARTS=y > > CONFIG_MTDIDS_DEFAULT="nor0=ff800000.flash,nand0=e1000000.flash" > > > > CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:7m(dum),768k(BOOT-BIN),128k(BOOT-ENV),128k(BOOT-REDENV);e1000000.flash:-(ubi)" > > CONFIG_CMD_UBI=y > > +CONFIG_OF_CONTROL=y > > +CONFIG_DEFAULT_DEVICE_TREE="ids8313" > > CONFIG_BOOTCOUNT_LIMIT=y > > CONFIG_BOOTCOUNT_I2C=y > > +CONFIG_DM_GPIO=y > > +CONFIG_MPC8XXX_GPIO=y > > # CONFIG_MMC is not set > > CONFIG_MTD_NOR_FLASH=y > > CONFIG_FLASH_CFI_DRIVER=y > > @@ -161,5 +165,5 @@ CONFIG_TSEC_ENET=y > > # CONFIG_PCI is not set > > CONFIG_SYS_NS16550=y > > CONFIG_SPI=y > > +CONFIG_DM_SPI=y > > CONFIG_MPC8XXX_SPI=y > > -CONFIG_OF_LIBFDT=y > > > > -- > DENX Software Engineering GmbH, Managing Director: Wolfgang Denk > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot