On 6/19/19 4:53 PM, Lukasz Majewski wrote:
> On Wed, 19 Jun 2019 16:32:57 +0200
> Marek Vasut <ma...@denx.de> wrote:
>
>> On 6/19/19 4:19 PM, Lukasz Majewski wrote:
>>> Hi Marek,
>>>
>>>> On 6/19/19 2:27 PM, Lukasz Majewski wrote:
>>>>> Those properties are U-Boot specific as the mxs gpio Linux driver
>>>>> (up to version v5.1.11) is not supporting them.
>>>>>
>>>>> Signed-off-by: Lukasz Majewski <lu...@denx.de>
>>>>
>>>> [...]
>>>>
>>>>> +&gpio4 {
>>>>> + gpio-ranges = <&pinctrl 120 0 21>;
>>>>
>>>> Are you sure the GPIO controller offset is 120 here ? Shouldn't
>>>> that be 0 , while the pin controller offset should be 120 ? Some
>>>> for the others ?
>>>
>>> Please find following excerpt from the documentation [1]:
>>>
>>> The format is: <[pin controller phandle], [GPIO controller offset],
>>> [pin controller offset], [number of pins]>;
>>>
>>> Example:
>>>
>>> gpio-ranges = <&foo 0 20 10>, <&bar 10 50 20>;
>>>
>>> This means:
>>> - pins 20..29 on pin controller "foo" is mapped to GPIO line 0..9
>>> and
>>> - pins 50..69 on pin controller "bar" is mapped to GPIO line 10..29
>>>
>>>
>>> The 120 is the GPIO controller offset (logical one) [*] and
>>> corresponds to the final GPIO number.
>>>
>>> Then we do have the "pin controller offset" which is the pin number
>>> start index per controller (like gpio0, gpio1, gpioN). In my case
>>> it is always 0.
>>
>> I think you have these two swapped. The pin controller is the
>> super-node here, hence each GPIO block is at offset N in the pin
>> controller pin space. Each GPIO block then has GPIOs, which either
>> start from 0 or M within the GPIO block pin space (in MXS case, this
>> is always 0).
>
> Yes, correct. This shall be <&pinctrl 0 120 21>
>
> I will prepare v6.
And update the GPIO controller driver accordingly.
--
Best regards,
Marek Vasut
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