This commit provides support for Ronetix GmbH i.MX7-CM board.

Supported peripherals: ETH, SD, eMMC, USB, I2C EEPROM, PMIC,
QSPI Nor Flash

U-boot console output:

U-Boot 2019.07-rc4-00358-g1f83431f00-dirty (Jul 05 2019-13:55:21 +0200)

CPU:   Freescale i.MX7D rev1.2 1000 MHz (running at 792 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 48C
Reset cause: POR
Model: Ronetix i.MX7-CM Board
Board: i.MX7-CM in secure mode
DRAM:  512 MiB
PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... OK
In:    serial
Out:   serial
Err:   serial
Net:   eth0: ethernet@30be0000

Signed-off-by: Ilko Iliev <il...@ronetix.at>
---
 arch/arm/dts/Makefile              |   3 +-
 arch/arm/dts/imx7-cm.dts           | 540 +++++++++++++++++++++++++++++
 arch/arm/mach-imx/mx7/Kconfig      |   8 +
 board/ronetix/imx7-cm/Kconfig      |  12 +
 board/ronetix/imx7-cm/MAINTAINERS  |   6 +
 board/ronetix/imx7-cm/Makefile     |   4 +
 board/ronetix/imx7-cm/imx7-cm.c    | 207 +++++++++++
 board/ronetix/imx7-cm/imximage.cfg | 103 ++++++
 configs/imx7_cm_defconfig          |  99 ++++++
 include/configs/imx7-cm.h          | 204 +++++++++++
 10 files changed, 1185 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/imx7-cm.dts
 create mode 100644 board/ronetix/imx7-cm/Kconfig
 create mode 100644 board/ronetix/imx7-cm/MAINTAINERS
 create mode 100644 board/ronetix/imx7-cm/Makefile
 create mode 100644 board/ronetix/imx7-cm/imx7-cm.c
 create mode 100644 board/ronetix/imx7-cm/imximage.cfg
 create mode 100644 configs/imx7_cm_defconfig
 create mode 100644 include/configs/imx7-cm.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 68f17c1e22..3df978f790 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -605,7 +605,8 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
        imx7-colibri-rawnand.dtb \
        imx7s-warp.dtb \
        imx7d-pico-pi.dtb \
-       imx7d-pico-hobbit.dtb
+       imx7d-pico-hobbit.dtb \
+       imx7-cm.dtb
 
 
 dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
diff --git a/arch/arm/dts/imx7-cm.dts b/arch/arm/dts/imx7-cm.dts
new file mode 100644
index 0000000000..529b5f3b13
--- /dev/null
+++ b/arch/arm/dts/imx7-cm.dts
@@ -0,0 +1,540 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017 NXP
+ */
+
+/dts-v1/;
+
+#include "imx7d.dtsi"
+
+&fec1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_enet1>;
+       pinctrl-assert-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
+       assigned-clocks = <&clks IMX7D_ENET_PHY_REF_ROOT_SRC>,
+                         <&clks IMX7D_ENET_AXI_ROOT_SRC>,
+                         <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
+                         <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
+                         <&clks IMX7D_ENET_AXI_ROOT_CLK>;
+       assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_25M_CLK>,
+                                <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
+                                <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+       assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>;
+       phy-mode = "rgmii";
+       phy-handle = <&ethphy0>;
+       fsl,magic-packet;
+       status = "okay";
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ethphy0: ethernet-phy@0 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <1>;
+               };
+       };
+};
+
+/ {
+       model = "Ronetix i.MX7-CM Board";
+       compatible = "fsl,imx7d-sdb", "fsl,imx7d";
+
+       regulators {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               reg_usb_otg1_vbus: regulator@0 {
+                       compatible = "regulator-fixed";
+                       reg = <0>;
+                       regulator-name = "usb_otg1_vbus";
+                       regulator-min-microvolt = <5000000>;
+                       regulator-max-microvolt = <5000000>;
+                       gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+               };
+
+               reg_usb_otg2_vbus: regulator@1 {
+                       compatible = "regulator-fixed";
+                       reg = <1>;
+                       regulator-name = "usb_otg2_vbus";
+                       regulator-min-microvolt = <5000000>;
+                       regulator-max-microvolt = <5000000>;
+                       gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+               };
+
+               reg_sd1_vmmc: regulator@3 {
+                       compatible = "regulator-fixed";
+                       regulator-name = "VDD_SD1";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+                       gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+                       startup-delay-us = <200000>;
+                       enable-active-high;
+               };
+       };
+};
+
+&iomuxc {
+       imx7d-sdb {
+                       pinctrl_enet1: enet1grp {
+                       fsl,pins = <
+                               MX7D_PAD_GPIO1_IO10__ENET1_MDIO                 
        0x3
+                               MX7D_PAD_GPIO1_IO11__ENET1_MDC                  
        0x3
+                               MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC       
0x1
+                               MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0       
0x1
+                               MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1       
0x1
+                               MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2       
0x1
+                               MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3       
0x1
+                               MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 
0x1
+                               MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC       
0x1
+                               MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0       
0x1
+                               MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1       
0x1
+                               MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2       
0x1
+                               MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3       
0x1
+                               MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 
0x1
+                       >;
+               };
+               
+               pinctrl_enet2: enet2grp {
+                       fsl,pins = <
+
+                               MX7D_PAD_GPIO1_IO14__ENET2_MDIO                 
        0x3
+                               MX7D_PAD_GPIO1_IO15__ENET2_MDC                  
        0x3
+                               MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC             
        0x1
+                               MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0            
0x1
+                               MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1            
0x1
+                               MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2            
0x1
+                               MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3             
        0x1
+                               MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL          
0x1
+                               MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC            
0x1
+                               MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0            
0x1
+                               MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1             
        0x1
+                               MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2             
        0x1
+                               MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3            
0x1
+                               MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL         
0x1
+                       >;
+               };
+               
+               pinctrl_spi1: spi1grp {
+                       fsl,pins = <
+                               MX7D_PAD_GPIO1_IO09__GPIO1_IO9  0x59
+                               MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
+                               MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
+                       >;
+               };
+
+               pinctrl_i2c1: i2c1grp {
+                       fsl,pins = <
+                               MX7D_PAD_I2C1_SDA__I2C1_SDA     0x4000007f
+                               MX7D_PAD_I2C1_SCL__I2C1_SCL     0x4000007f
+                       >;
+               };
+
+               pinctrl_i2c2: i2c2grp {
+                       fsl,pins = <
+                               MX7D_PAD_I2C2_SDA__I2C2_SDA     0x4000007f
+                               MX7D_PAD_I2C2_SCL__I2C2_SCL     0x4000007f
+                       >;
+               };
+
+               pinctrl_i2c3: i2c3grp {
+                       fsl,pins = <
+                               MX7D_PAD_I2C3_SDA__I2C3_SDA     0x4000007f
+                               MX7D_PAD_I2C3_SCL__I2C3_SCL     0x4000007f
+                       >;
+               };
+
+               pinctrl_i2c4: i2c4grp {
+                       fsl,pins = <
+                               MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
+                               MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
+                       >;
+               };
+
+               pinctrl_usbotg2_pwr_1: usbotg2-1 {
+                       fsl,pins = <
+                               MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14
+                       >;
+               };
+               
+               pinctrl_usdhc1_gpio: usdhc1_gpiogrp {
+                       fsl,pins = <
+                               MX7D_PAD_SD1_CD_B__GPIO5_IO0            0x59 /* 
CD */
+                               MX7D_PAD_SD1_WP__GPIO5_IO1                      
0x59 /* WP */
+                               MX7D_PAD_SD1_RESET_B__GPIO5_IO2         0x59 /* 
vmmc */
+                               MX7D_PAD_GPIO1_IO08__SD1_VSELECT        0x59 /* 
VSELECT */
+                       >;
+               };
+
+               pinctrl_usdhc1: usdhc1grp {
+                       fsl,pins = <
+                               MX7D_PAD_SD1_CMD__SD1_CMD                       
0x59
+                               MX7D_PAD_SD1_CLK__SD1_CLK                       
0x19
+                               MX7D_PAD_SD1_DATA0__SD1_DATA0           0x59
+                               MX7D_PAD_SD1_DATA1__SD1_DATA1           0x59
+                               MX7D_PAD_SD1_DATA2__SD1_DATA2           0x59
+                               MX7D_PAD_SD1_DATA3__SD1_DATA3           0x59
+                       >;
+               };
+
+               pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
+                       fsl,pins = <
+                               MX7D_PAD_SD1_CMD__SD1_CMD                       
0x5a
+                               MX7D_PAD_SD1_CLK__SD1_CLK                       
0x1a
+                               MX7D_PAD_SD1_DATA0__SD1_DATA0           0x5a
+                               MX7D_PAD_SD1_DATA1__SD1_DATA1           0x5a
+                               MX7D_PAD_SD1_DATA2__SD1_DATA2           0x5a
+                               MX7D_PAD_SD1_DATA3__SD1_DATA3           0x5a
+                       >;
+               };
+
+               pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
+                       fsl,pins = <
+                               MX7D_PAD_SD1_CMD__SD1_CMD                       
0x5b
+                               MX7D_PAD_SD1_CLK__SD1_CLK                       
0x1b
+                               MX7D_PAD_SD1_DATA0__SD1_DATA0           0x5b
+                               MX7D_PAD_SD1_DATA1__SD1_DATA1           0x5b
+                               MX7D_PAD_SD1_DATA2__SD1_DATA2           0x5b
+                               MX7D_PAD_SD1_DATA3__SD1_DATA3           0x5b
+                       >;
+               };
+
+               pinctrl_usdhc2: usdhc2grp {
+                       fsl,pins = <
+                               MX7D_PAD_SD2_CMD__SD2_CMD               0x59
+                               MX7D_PAD_SD2_CLK__SD2_CLK               0x19
+                               MX7D_PAD_SD2_DATA0__SD2_DATA0           0x59
+                               MX7D_PAD_SD2_DATA1__SD2_DATA1           0x59
+                               MX7D_PAD_SD2_DATA2__SD2_DATA2           0x59
+                               MX7D_PAD_SD2_DATA3__SD2_DATA3           0x59
+                               MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21        0x19 /* 
WL_REG_ON */
+                               MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20        0x19 /* 
WL_HOST_WAKE */
+                       >;
+               };
+
+               pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
+                       fsl,pins = <
+                               MX7D_PAD_SD2_CMD__SD2_CMD                       
0x5a
+                               MX7D_PAD_SD2_CLK__SD2_CLK                       
0x1a
+                               MX7D_PAD_SD2_DATA0__SD2_DATA0           0x5a
+                               MX7D_PAD_SD2_DATA1__SD2_DATA1           0x5a
+                               MX7D_PAD_SD2_DATA2__SD2_DATA2           0x5a
+                               MX7D_PAD_SD2_DATA3__SD2_DATA3           0x5a
+                       >;
+               };
+
+               pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
+                       fsl,pins = <
+                               MX7D_PAD_SD2_CMD__SD2_CMD                       
0x5b
+                               MX7D_PAD_SD2_CLK__SD2_CLK                       
0x1b
+                               MX7D_PAD_SD2_DATA0__SD2_DATA0           0x5b
+                               MX7D_PAD_SD2_DATA1__SD2_DATA1           0x5b
+                               MX7D_PAD_SD2_DATA2__SD2_DATA2           0x5b
+                               MX7D_PAD_SD2_DATA3__SD2_DATA3           0x5b
+                       >;
+               };
+
+               pinctrl_usdhc3: usdhc3grp {
+                       fsl,pins = <
+                               MX7D_PAD_SD3_CMD__SD3_CMD                       
0x59
+                               MX7D_PAD_SD3_CLK__SD3_CLK                       
0x19
+                               MX7D_PAD_SD3_DATA0__SD3_DATA0           0x59
+                               MX7D_PAD_SD3_DATA1__SD3_DATA1           0x59
+                               MX7D_PAD_SD3_DATA2__SD3_DATA2           0x59
+                               MX7D_PAD_SD3_DATA3__SD3_DATA3           0x59
+                               MX7D_PAD_SD3_DATA4__SD3_DATA4           0x59
+                               MX7D_PAD_SD3_DATA5__SD3_DATA5           0x59
+                               MX7D_PAD_SD3_DATA6__SD3_DATA6           0x59
+                               MX7D_PAD_SD3_DATA7__SD3_DATA7           0x59
+                               MX7D_PAD_SD3_STROBE__SD3_STROBE     0x19
+                       >;
+               };
+
+               pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
+                       fsl,pins = <
+                               MX7D_PAD_SD3_CMD__SD3_CMD                       
0x5a
+                               MX7D_PAD_SD3_CLK__SD3_CLK                       
0x1a
+                               MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5a
+                               MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5a
+                               MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5a
+                               MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5a
+                               MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5a
+                               MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5a
+                               MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5a
+                               MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5a
+                               MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1a
+                       >;
+               };
+
+               pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
+                       fsl,pins = <
+                               MX7D_PAD_SD3_CMD__SD3_CMD                       
0x5b
+                               MX7D_PAD_SD3_CLK__SD3_CLK                       
0x1b
+                               MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5b
+                               MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5b
+                               MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5b
+                               MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5b
+                               MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5b
+                               MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5b
+                               MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5b
+                               MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5b
+                               MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1b
+                       >;
+               };
+       };
+
+       qspi1 {
+               pinctrl_qspi1_1: qspi1grp_1 {
+                       fsl,pins = <
+                               MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0      0x51
+                               MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1      0x51
+                               MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2      0x51
+                               MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3      0x51
+                               MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK       0x51
+                               MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B      0x51
+                       >;
+               };
+       };
+};
+
+&iomuxc_lpsr {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_hog_2 &pinctrl_usbotg2_pwr_2>;
+
+       imx7d-sdb {
+               pinctrl_hog_2: hoggrp-2 {
+                       fsl,pins = <
+                               MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5             
        0x14
+                       >;
+               };
+
+               pinctrl_pwm1: pwm1grp {
+                       fsl,pins = <
+                               MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT              
        0x30
+                       >;
+               };
+
+               pinctrl_usbotg2_pwr_2: usbotg2-2 {
+                       fsl,pins = <
+                               MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7             
0x14
+                       >;
+               };
+
+               pinctrl_wdog: wdoggrp {
+                       fsl,pins = <
+                               MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B          
0x74
+                       >;
+               };
+
+               pinctrl_enet2_epdc0_en: enet2_epdc0_grp {
+                       fsl,pins = <
+                               MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4         
0x80000000
+                       >;
+               };
+
+               pinctrl_sai3_mclk: sai3grp_mclk {
+                      fsl,pins = <
+                              MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK          0x1f
+                      >;
+              };
+       };
+};
+
+&i2c1 {
+       clock-frequency = <100000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c1>;
+       status = "okay";
+
+       i2c_eeprom: i2c_eeprom@50 {
+               compatible = "microchip,24lc512";
+               reg = <0x50>;
+               pagesize = <128>;
+       };
+
+       pmic: pfuze3000@08 {
+               compatible = "fsl,pfuze3000";
+               reg = <0x08>;
+
+               regulators {
+                       sw1a_reg: sw1a {
+                               regulator-min-microvolt = <700000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                               regulator-ramp-delay = <6250>;
+                       };
+
+                       /* use sw1c_reg to align with pfuze100/pfuze200 */
+                       sw1c_reg: sw1b {
+                               regulator-min-microvolt = <700000>;
+                               regulator-max-microvolt = <1475000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                               regulator-ramp-delay = <6250>;
+                       };
+
+                       sw2_reg: sw2 {
+                               regulator-min-microvolt = <1500000>;
+                               regulator-max-microvolt = <1850000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       sw3a_reg: sw3 {
+                               regulator-min-microvolt = <900000>;
+                               regulator-max-microvolt = <1650000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       swbst_reg: swbst {
+                               regulator-min-microvolt = <5000000>;
+                               regulator-max-microvolt = <5150000>;
+                       };
+
+                       snvs_reg: vsnvs {
+                               regulator-min-microvolt = <1000000>;
+                               regulator-max-microvolt = <3000000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       vref_reg: vrefddr {
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       vgen1_reg: vldo1 {
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                       };
+
+                       vgen2_reg: vldo2 {
+                               regulator-min-microvolt = <800000>;
+                               regulator-max-microvolt = <1550000>;
+                               regulator-always-on;
+                       };
+
+                       vgen3_reg: vccsd {
+                               regulator-min-microvolt = <2850000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                       };
+
+                       vgen4_reg: v33 {
+                               regulator-min-microvolt = <2850000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                       };
+
+                       vgen5_reg: vldo3 {
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                       };
+
+                       vgen6_reg: vldo4 {
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                       };
+               };
+       };
+};
+
+&i2c2 {
+       clock-frequency = <100000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c2>;
+       status = "okay";
+};
+
+&i2c3 {
+       clock-frequency = <100000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c3>;
+       status = "okay";
+};
+
+&i2c4 {
+       clock-frequency = <100000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c4>;
+       status = "okay";
+};
+
+&usbotg1 {
+       vbus-supply = <&reg_usb_otg1_vbus>;
+       srp-disable;
+       hnp-disable;
+       adp-disable;
+       status = "okay";
+};
+
+&usbotg2 {
+       vbus-supply = <&reg_usb_otg2_vbus>;
+       dr_mode = "host";
+       status = "okay";
+};
+
+&usdhc1 {
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
+       pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
+       pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
+       cd-gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
+       wp-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
+       vmmc-supply = <&reg_sd1_vmmc>;
+       fsl,tuning-start-tap = <20>;
+       fsl,tuning-step= <2>;
+       status = "okay";
+};
+
+&usdhc2 {
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc2>;
+       pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+       pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+       non-removable;
+       fsl,tuning-start-tap = <20>;
+       fsl,tuning-step= <2>;
+       status = "okay";
+};
+
+&usdhc3 {
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc3>;
+       pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+       pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+       bus-width = <8>;
+       non-removable;
+       fsl,tuning-start-tap = <20>;
+       fsl,tuning-step= <2>;
+       status = "okay";
+};
+
+/* disable epdc, conflict with qspi */
+&epdc {
+       status = "disabled";
+};
+
+&qspi1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_qspi1_1>;
+       status = "okay";
+       ddrsmp=<0>;
+
+       flash0: mx25l25645g@0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "macronix,mx25l25645g";
+               /* take off one dummy cycle */
+               spi-nor,ddr-quad-read-dummy = <5>;
+               reg = <0>;
+       };
+};
diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig
index 232f33285d..2058d97b2c 100644
--- a/arch/arm/mach-imx/mx7/Kconfig
+++ b/arch/arm/mach-imx/mx7/Kconfig
@@ -60,6 +60,13 @@ config TARGET_COLIBRI_IMX7
        select DM_THERMAL
        imply CMD_DM
 
+config TARGET_IMX7_CM
+       bool "imx7-cm"
+       select BOARD_LATE_INIT
+       select DM
+       select DM_THERMAL
+       select MX7D
+       imply CMD_DM
 endchoice
 
 config SYS_SOC
@@ -70,5 +77,6 @@ source "board/freescale/mx7dsabresd/Kconfig"
 source "board/technexion/pico-imx7d/Kconfig"
 source "board/toradex/colibri_imx7/Kconfig"
 source "board/warp7/Kconfig"
+source "board/ronetix/imx7-cm/Kconfig"
 
 endif
diff --git a/board/ronetix/imx7-cm/Kconfig b/board/ronetix/imx7-cm/Kconfig
new file mode 100644
index 0000000000..ef7565419f
--- /dev/null
+++ b/board/ronetix/imx7-cm/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_IMX7_CM
+
+config SYS_BOARD
+       default "imx7-cm"
+
+config SYS_VENDOR
+       default "ronetix"
+
+config SYS_CONFIG_NAME
+       default "imx7-cm"
+
+endif
diff --git a/board/ronetix/imx7-cm/MAINTAINERS 
b/board/ronetix/imx7-cm/MAINTAINERS
new file mode 100644
index 0000000000..5faa2c5c8b
--- /dev/null
+++ b/board/ronetix/imx7-cm/MAINTAINERS
@@ -0,0 +1,6 @@
+IMX7-CM BOARD
+M:     Ilko Iliev <il...@ronetix.at>
+S:     Maintained
+F:     board/ronetix/imx7-cm/
+F:     include/configs/imx7-cm.h
+F:     configs/imx7-cm_defconfig
diff --git a/board/ronetix/imx7-cm/Makefile b/board/ronetix/imx7-cm/Makefile
new file mode 100644
index 0000000000..34021b00fd
--- /dev/null
+++ b/board/ronetix/imx7-cm/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2015 Freescale Semiconductor, Inc.
+
+obj-y  := imx7-cm.o
diff --git a/board/ronetix/imx7-cm/imx7-cm.c b/board/ronetix/imx7-cm/imx7-cm.c
new file mode 100644
index 0000000000..9890e35a41
--- /dev/null
+++ b/board/ronetix/imx7-cm/imx7-cm.c
@@ -0,0 +1,207 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx7-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/io.h>
+#include <linux/sizes.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze3000_pmic.h>
+#include <i2c.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/crm_regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* status LED */
+#define GPIO_LED_STATUS                        IMX_GPIO_NR(2, 7)
+
+/* reset PHY */
+#define GPIO_PHY_RESET                 IMX_GPIO_NR(2, 4)
+
+/* LCD back light enable: 1- ON, 0 - OFF */
+#define GPIO_LCD_BL_EN                 IMX_GPIO_NR(1, 13)
+
+/* LCD back light PWM */
+#define GPIO_LCD_BL_PWM                        IMX_GPIO_NR(1, 1)
+
+#define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | \
+       PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+       gd->ram_size = PHYS_SDRAM_SIZE;
+
+       return 0;
+}
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+       MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+       MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+       MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+       imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+       if (devno == 2)
+               devno--;
+
+       return devno;
+}
+
+int mmc_map_to_kernel_blk(int dev_no)
+{
+       if (dev_no == 1)
+               dev_no++;
+
+       return dev_no;
+}
+
+#ifdef CONFIG_FEC_MXC
+static int setup_fec(void)
+{
+       struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
+               = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
+
+       int ret;
+       unsigned int gpio = GPIO_PHY_RESET;
+
+       ret = gpio_request(gpio, "fec_rst");
+       if (ret && ret != -EBUSY) {
+               printf("gpio: requesting pin %u failed\n", gpio);
+               return ret;
+       }
+
+       gpio_direction_output(gpio, 0);
+       udelay(500);
+       gpio_direction_output(gpio, 1);
+       udelay(10000);
+
+       /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
+       clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
+               (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
+                IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
+
+       /* Use 125M anatop REF_CLK2 for ENET2, clear gpr1[14], gpr1[18]*/
+       clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
+               (IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK |
+                IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK), 0);
+
+       return set_clk_enet(ENET_125MHZ);
+}
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+int board_qspi_init(void)
+{
+       /* Set the clock */
+       set_clk_qspi();
+
+       return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+       setup_iomux_uart();
+
+       return 0;
+}
+
+int board_init(void)
+{
+       /* address of boot parameters */
+       gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+       /* turn ON the status LED */
+       gpio_request(GPIO_LED_STATUS, "LED status");
+       gpio_direction_output(GPIO_LED_STATUS, 0);
+
+#ifdef CONFIG_FEC_MXC
+       setup_fec();
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+       board_qspi_init();
+#endif
+
+       return 0;
+}
+
+#ifdef CONFIG_DM_PMIC
+int power_init_board(void)
+{
+       struct udevice *dev;
+       int ret, dev_id, rev_id;
+
+       ret = pmic_get("pfuze3000", &dev);
+       if (ret == -ENODEV)
+               return 0;
+       if (ret != 0)
+               return ret;
+
+       dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
+       rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
+       printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
+
+       pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1);
+
+       /*
+        * Set the voltage of VLDO4 output to 2.8V which feeds
+        * the MIPI DSI and MIPI CSI inputs.
+        */
+       pmic_clrsetbits(dev, PFUZE3000_VLD4CTL, 0xF, 0xA);
+
+       return 0;
+}
+#endif
+
+int board_late_init(void)
+{
+       struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+       imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+       set_wdog_reset(wdog);
+
+       /*
+        * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
+        * since we use PMIC_PWRON to reset the board.
+        */
+       clrsetbits_le16(&wdog->wcr, 0, 0x10);
+
+       return 0;
+}
+
+int checkboard(void)
+{
+       char *mode;
+
+       if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
+               mode = "secure";
+       else
+               mode = "non-secure";
+
+       printf("Board: i.MX7-CM in %s mode\n", mode);
+
+       return 0;
+}
diff --git a/board/ronetix/imx7-cm/imximage.cfg 
b/board/ronetix/imx7-cm/imximage.cfg
new file mode 100644
index 0000000000..8021aa28e2
--- /dev/null
+++ b/board/ronetix/imx7-cm/imximage.cfg
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : sd
+ */
+
+BOOT_FROM      sd
+
+/*
+ * Secure boot support
+ */
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *     Addr-type register length (1,2 or 4 bytes)
+ *     Address   absolute address of the register
+ *     value     value to be stored in the register
+ */
+
+DATA 4 0x30340004 0x4F400005
+/* Clear then set bit30 to ensure exit from DDR retention */
+DATA 4 0x30360388 0x40000000
+DATA 4 0x30360384 0x40000000
+
+DATA 4 0x30391000 0x00000002
+DATA 4 0x307a0000 0x01040001
+DATA 4 0x307a01a0 0x80400003
+DATA 4 0x307a01a4 0x00100020
+DATA 4 0x307a01a8 0x80100004
+DATA 4 0x307a0064 0x00400046
+DATA 4 0x307a0490 0x00000001
+DATA 4 0x307a00d0 0x00020083
+DATA 4 0x307a00d4 0x00690000
+DATA 4 0x307a00dc 0x09300004
+DATA 4 0x307a00e0 0x04080000
+DATA 4 0x307a00e4 0x00100004
+DATA 4 0x307a00f4 0x0000033f
+DATA 4 0x307a0100 0x09081109
+DATA 4 0x307a0104 0x0007020d
+DATA 4 0x307a0108 0x03040407
+DATA 4 0x307a010c 0x00002006
+DATA 4 0x307a0110 0x04020205
+DATA 4 0x307a0114 0x03030202
+DATA 4 0x307a0120 0x00000803
+DATA 4 0x307a0180 0x00800020
+DATA 4 0x307a0184 0x02000100
+DATA 4 0x307a0190 0x02098204
+DATA 4 0x307a0194 0x00030303
+DATA 4 0x307a0200 0x00000016
+DATA 4 0x307a0204 0x00080808
+DATA 4 0x307a0210 0x00000f0f
+DATA 4 0x307a0214 0x07070707
+DATA 4 0x307a0218 0x0f070707
+DATA 4 0x307a0240 0x06000604
+DATA 4 0x307a0244 0x00000001
+DATA 4 0x30391000 0x00000000
+DATA 4 0x30790000 0x17420f40
+DATA 4 0x30790004 0x10210100
+DATA 4 0x30790010 0x00060807
+DATA 4 0x307900b0 0x1010007e
+DATA 4 0x3079009c 0x00000b24
+DATA 4 0x30790020 0x0A0A0A0A
+DATA 4 0x30790030 0x06060606
+DATA 4 0x30790050 0x01000010
+DATA 4 0x30790050 0x00000010
+
+DATA 4 0x307900c0 0x0e407304
+DATA 4 0x307900c0 0x0e447304
+DATA 4 0x307900c0 0x0e447306
+
+CHECK_BITS_SET 4 0x307900c4 0x1
+
+DATA 4 0x307900c0 0x0e407304
+
+DATA 4 0x30384130 0x00000000
+DATA 4 0x30340020 0x00000178
+DATA 4 0x30384130 0x00000002
+DATA 4 0x30790018 0x0000000f
+
+CHECK_BITS_SET 4 0x307a0004 0x1
diff --git a/configs/imx7_cm_defconfig b/configs/imx7_cm_defconfig
new file mode 100644
index 0000000000..d816072da6
--- /dev/null
+++ b/configs/imx7_cm_defconfig
@@ -0,0 +1,99 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX7=y
+CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_TARGET_IMX7_CM=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
+# CONFIG_ARMV7_VIRT is not set
+CONFIG_IMX_RDC=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ronetix/imx7-cm/imximage.cfg"
+CONFIG_QSPI_BOOT=y
+CONFIG_FSL_QSPI=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx7-cm"
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_FSL_ESDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=50000000
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_VIDEO=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_ERRNO_STR=y
+CONFIG_DM_ETH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FSL_FASTBOOT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_EFI_PARTITION=y
diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h
new file mode 100644
index 0000000000..80eb8b9dac
--- /dev/null
+++ b/include/configs/imx7-cm.h
@@ -0,0 +1,204 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Ronetix i.MX7-CM board.
+ */
+
+#ifndef __IMX7CM_CONFIG_H
+#define __IMX7CM_CONFIG_H
+
+#include "mx7_common.h"
+
+#define PHYS_SDRAM_SIZE                                SZ_512M
+
+#define CONFIG_MXC_UART_BASE           UART1_IPS_BASE_ADDR
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN          (32 * SZ_1M)
+
+/* Network */
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_XCV_TYPE         RGMII
+#define CONFIG_ETHPRIME             "FEC"
+
+/* ENET1 */
+#define IMX_FEC_BASE                           ENET_IPS_BASE_ADDR
+
+/* MMC Config*/
+#define CONFIG_SYS_FSL_ESDHC_ADDR   0
+
+#undef CONFIG_BOOTM_NETBSD
+#undef CONFIG_BOOTM_PLAN9
+#undef CONFIG_BOOTM_RTEMS
+
+/* I2C configs */
+/* I2C EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED                   100000
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART   1
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SYS_FSL_QSPI_AHB
+#define CONFIG_SF_DEFAULT_CS           0
+#define FSL_QSPI_FLASH_NUM                     1
+#define FSL_QSPI_FLASH_SIZE                    SZ_32M
+#define QSPI0_BASE_ADDR                                QSPI1_IPS_BASE_ADDR
+#define QSPI0_AMBA_BASE                                QSPI0_ARB_BASE_ADDR
+#endif
+
+#ifdef CONFIG_IMX_BOOTAUX
+/* Set to QSPI1 A flash at default */
+#define CONFIG_SYS_AUXCORE_BOOTDATA 0x60000000
+
+#define UPDATE_M4_ENV \
+       "m4image=m4_qspi.bin\0" \
+       "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" 
\
+       "update_m4_from_sd=" \
+               "if sf probe 0:0; then " \
+                       "if run loadm4image; then " \
+                               "setexpr fw_sz ${filesize} + 0xffff; " \
+                               "setexpr fw_sz ${fw_sz} / 0x10000; "    \
+                               "setexpr fw_sz ${fw_sz} * 0x10000; "    \
+                               "sf erase 0x0 ${fw_sz}; " \
+                               "sf write ${loadaddr} 0x0 ${filesize}; " \
+                       "fi; " \
+               "fi\0" \
+       "m4boot=sf probe 0:0; bootaux 
"__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
+#else
+#define UPDATE_M4_ENV ""
+#endif
+
+#define CONFIG_MFG_ENV_SETTINGS \
+       "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
+               "rdinit=/linuxrc " \
+               "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
+               "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF 
"\
+               "g_mass_storage.iSerialNumber=\"\" "\
+               "clk_ignore_unused "\
+               "\0" \
+       "initrd_addr=0x83800000\0" \
+       "initrd_high=0xffffffff\0" \
+       "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} 
${fdt_addr};\0" \
+
+#define CONFIG_DFU_ENV_SETTINGS \
+       "dfu_alt_info=image raw 0 0x800000;"\
+               "u-boot raw 0 0x4000;"\
+               "bootimg part 0 1;"\
+               "rootfs part 0 2\0" \
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+       UPDATE_M4_ENV \
+       CONFIG_MFG_ENV_SETTINGS \
+       CONFIG_DFU_ENV_SETTINGS \
+       "script=boot.scr\0" \
+       "image=zImage\0" \
+       "console=ttymxc0\0" \
+       "fdt_high=0xffffffff\0" \
+       "initrd_high=0xffffffff\0" \
+       "fdt_file=imx7-cm.dtb\0" \
+       "fdt_addr=0x83000000\0" \
+       "boot_fdt=try\0" \
+       "ip_dyn=yes\0" \
+       "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+       "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+       "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+       "mmcautodetect=yes\0" \
+       "mmcargs=setenv bootargs console=${console},${baudrate} " \
+               "root=${mmcroot}\0" \
+       "loadbootscript=" \
+               "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+       "bootscript=echo Running bootscript from mmc ...; " \
+               "source\0" \
+       "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+       "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+       "mmcboot=echo Booting from mmc ...; " \
+               "run mmcargs; " \
+               "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+                       "if run loadfdt; then " \
+                               "bootz ${loadaddr} - ${fdt_addr}; " \
+                       "else " \
+                               "if test ${boot_fdt} = try; then " \
+                                       "bootz; " \
+                               "else " \
+                                       "echo WARN: Cannot load the DT; " \
+                               "fi; " \
+                       "fi; " \
+               "else " \
+                       "bootz; " \
+               "fi;\0" \
+       "netargs=setenv bootargs console=${console},${baudrate} " \
+               "root=/dev/nfs " \
+       "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+               "netboot=echo Booting from net ...; " \
+               "run netargs; " \
+               "if test ${ip_dyn} = yes; then " \
+                       "setenv get_cmd dhcp; " \
+               "else " \
+                       "setenv get_cmd tftp; " \
+               "fi; " \
+               "${get_cmd} ${image}; " \
+               "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+                       "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+                               "bootz ${loadaddr} - ${fdt_addr}; " \
+                       "else " \
+                               "if test ${boot_fdt} = try; then " \
+                                       "bootz; " \
+                               "else " \
+                                       "echo WARN: Cannot load the DT; " \
+                               "fi; " \
+                       "fi; " \
+               "else " \
+                       "bootz; " \
+               "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+          "mmc dev ${mmcdev};" \
+          "mmc dev ${mmcdev}; if mmc rescan; then " \
+                  "if run loadbootscript; then " \
+                          "run bootscript; " \
+                  "else " \
+                          "if run loadimage; then " \
+                                  "run mmcboot; " \
+                          "else run netboot; " \
+                          "fi; " \
+                  "fi; " \
+          "else run netboot; fi"
+
+#define CONFIG_SYS_MEMTEST_START       0x80000000
+#define CONFIG_SYS_MEMTEST_END         (CONFIG_SYS_MEMTEST_START + 0x10000000)
+
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
+#define CONFIG_SYS_HZ                          1000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM                                     MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+       (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* environment organization */
+#define CONFIG_ENV_SIZE                                SZ_8K
+
+#define CONFIG_ENV_OFFSET                      (12 * SZ_64K)
+#define CONFIG_SYS_FSL_USDHC_NUM       2
+
+#define CONFIG_SYS_MMC_ENV_DEV         0   /* USDHC1 */
+#define CONFIG_SYS_MMC_ENV_PART                0       /* user area */
+#define CONFIG_MMCROOT                 "/dev/mmcblk0p2"  /* USDHC1 */
+
+/* USB Configs */
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+
+#define CONFIG_IMX_THERMAL
+#define CONFIG_USBD_HS
+
+#endif /* __CONFIG_H */
-- 
2.17.1

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