> Subject: [PATCH 4/4] mx6: Allow configuring the NoC registers on i.MX6QP
>
> The NoC registers on i.MX6QP needs to be configured, otherwise some
> usecases in the kernel behave incorrectly, such as rotation and resize.
>
> Currently the NoC registers are not configured in the kernel, so configure
> them
> in U-Boot like it is done in the NXP U-Boot tree.
>
> Signed-off-by: Fabio Estevam <feste...@gmail.com>
> ---
> arch/arm/mach-imx/mx6/soc.c | 32
> ++++++++++++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
> index e80f1d484b..8de42408c7 100644
> --- a/arch/arm/mach-imx/mx6/soc.c
> +++ b/arch/arm/mach-imx/mx6/soc.c
> @@ -365,6 +365,35 @@ static void init_bandgap(void)
> }
> }
>
> +static void noc_setup(void)
> +{
> + enable_ipu_clock();
> +
> + writel(0x80000201, 0xbb0608);
> + /* Bypass IPU1 QoS generator */
> + writel(0x00000002, 0x00bb048c);
> + /* Bypass IPU2 QoS generator */
> + writel(0x00000002, 0x00bb050c);
> + /* Bandwidth THR for of PRE0 */
> + writel(0x00000200, 0x00bb0690);
> + /* Bandwidth THR for of PRE1 */
> + writel(0x00000200, 0x00bb0710);
> + /* Bandwidth THR for of PRE2 */
> + writel(0x00000200, 0x00bb0790);
> + /* Bandwidth THR for of PRE3 */
> + writel(0x00000200, 0x00bb0810);
> + /* Saturation THR for of PRE0 */
> + writel(0x00000010, 0x00bb0694);
> + /* Saturation THR for of PRE1 */
> + writel(0x00000010, 0x00bb0714);
> + /* Saturation THR for of PRE2 */
> + writel(0x00000010, 0x00bb0794);
> + /* Saturation THR for of PRE */
> + writel(0x00000010, 0x00bb0814);
> +
> + disable_ipu_clock();
> +}
> +
> int arch_cpu_init(void)
> {
> struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> @@ -442,6 +471,9 @@ int arch_cpu_init(void)
>
> init_src();
>
> + if (is_mx6dqp())
> + noc_setup();
> +
> return 0;
> }
Reviewed-by: Peng Fan <peng....@nxp.com>
>
> --
> 2.17.1
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