On Thu, Jul 11, 2019 at 12:13 PM Bin Meng <bmeng...@gmail.com> wrote: > > This syncs csr.h with Linux kernel 5.2, and imports asm.h that > is required by csr.h. > > Signed-off-by: Bin Meng <bmeng...@gmail.com> > --- > > arch/riscv/include/asm/asm.h | 68 > ++++++++++++++++++++++++++++++++++++++++++++ > arch/riscv/include/asm/csr.h | 62 +++++++++++++++++++++++++++++----------- > 2 files changed, 114 insertions(+), 16 deletions(-) > create mode 100644 arch/riscv/include/asm/asm.h > > diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h > new file mode 100644 > index 0000000..5a02b7d > --- /dev/null > +++ b/arch/riscv/include/asm/asm.h > @@ -0,0 +1,68 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (C) 2015 Regents of the University of California > + */ > + > +#ifndef _ASM_RISCV_ASM_H > +#define _ASM_RISCV_ASM_H > + > +#ifdef __ASSEMBLY__ > +#define __ASM_STR(x) x > +#else > +#define __ASM_STR(x) #x > +#endif > + > +#if __riscv_xlen == 64 > +#define __REG_SEL(a, b) __ASM_STR(a) > +#elif __riscv_xlen == 32 > +#define __REG_SEL(a, b) __ASM_STR(b) > +#else > +#error "Unexpected __riscv_xlen" > +#endif > + > +#define REG_L __REG_SEL(ld, lw) > +#define REG_S __REG_SEL(sd, sw) > +#define SZREG __REG_SEL(8, 4) > +#define LGREG __REG_SEL(3, 2) > + > +#if __SIZEOF_POINTER__ == 8 > +#ifdef __ASSEMBLY__ > +#define RISCV_PTR .dword > +#define RISCV_SZPTR 8 > +#define RISCV_LGPTR 3 > +#else > +#define RISCV_PTR ".dword" > +#define RISCV_SZPTR "8" > +#define RISCV_LGPTR "3" > +#endif > +#elif __SIZEOF_POINTER__ == 4 > +#ifdef __ASSEMBLY__ > +#define RISCV_PTR .word > +#define RISCV_SZPTR 4 > +#define RISCV_LGPTR 2 > +#else > +#define RISCV_PTR ".word" > +#define RISCV_SZPTR "4" > +#define RISCV_LGPTR "2" > +#endif > +#else > +#error "Unexpected __SIZEOF_POINTER__" > +#endif > + > +#if (__SIZEOF_INT__ == 4) > +#define RISCV_INT __ASM_STR(.word) > +#define RISCV_SZINT __ASM_STR(4) > +#define RISCV_LGINT __ASM_STR(2) > +#else > +#error "Unexpected __SIZEOF_INT__" > +#endif > + > +#if (__SIZEOF_SHORT__ == 2) > +#define RISCV_SHORT __ASM_STR(.half) > +#define RISCV_SZSHORT __ASM_STR(2) > +#define RISCV_LGSHORT __ASM_STR(1) > +#else > +#error "Unexpected __SIZEOF_SHORT__" > +#endif > + > +#endif /* _ASM_RISCV_ASM_H */ > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h > index 644e6ba..1a6bcfc 100644 > --- a/arch/riscv/include/asm/csr.h > +++ b/arch/riscv/include/asm/csr.h > @@ -1,4 +1,4 @@ > -/* SPDX-License-Identifier: GPL-2.0 */ > +/* SPDX-License-Identifier: GPL-2.0-only */ > /* > * Copyright (C) 2015 Regents of the University of California > * > @@ -8,13 +8,14 @@ > #ifndef _ASM_RISCV_CSR_H > #define _ASM_RISCV_CSR_H > > +#include <asm/asm.h> > #include <linux/const.h> > > /* Status register flags */ > #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ > #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE > */ > #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ > -#define SR_SUM _AC(0x00040000, UL) /* Supervisor access User Memory > */ > +#define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access > */ > > #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ > #define SR_FS_OFF _AC(0x00000000, UL) > @@ -35,7 +36,7 @@ > #endif > > /* SATP flags */ > -#if __riscv_xlen == 32 > +#ifndef CONFIG_64BIT > #define SATP_PPN _AC(0x003FFFFF, UL) > #define SATP_MODE_32 _AC(0x80000000, UL) > #define SATP_MODE SATP_MODE_32 > @@ -45,10 +46,18 @@ > #define SATP_MODE SATP_MODE_39 > #endif > > -/* Interrupt Enable and Interrupt Pending flags */ > -#define MIE_MSIE _AC(0x00000008, UL) /* Software Interrupt Enable */ > -#define SIE_SSIE _AC(0x00000002, UL) /* Software Interrupt Enable */ > -#define SIE_STIE _AC(0x00000020, UL) /* Timer Interrupt Enable */ > +/* SCAUSE */ > +#define SCAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) > + > +#define IRQ_U_SOFT 0 > +#define IRQ_S_SOFT 1 > +#define IRQ_M_SOFT 3 > +#define IRQ_U_TIMER 4 > +#define IRQ_S_TIMER 5 > +#define IRQ_M_TIMER 7 > +#define IRQ_U_EXT 8 > +#define IRQ_S_EXT 9 > +#define IRQ_M_EXT 11 > > #define EXC_INST_MISALIGNED 0 > #define EXC_INST_ACCESS 1 > @@ -60,14 +69,35 @@ > #define EXC_LOAD_PAGE_FAULT 13 > #define EXC_STORE_PAGE_FAULT 15 > > -#ifndef __ASSEMBLY__ > +/* SIE (Interrupt Enable) and SIP (Interrupt Pending) flags */ > +#define MIE_MSIE (_AC(0x1, UL) << IRQ_M_SOFT) > +#define SIE_SSIE (_AC(0x1, UL) << IRQ_S_SOFT) > +#define SIE_STIE (_AC(0x1, UL) << IRQ_S_TIMER) > +#define SIE_SEIE (_AC(0x1, UL) << IRQ_S_EXT) > + > +#define CSR_CYCLE 0xc00 > +#define CSR_TIME 0xc01 > +#define CSR_INSTRET 0xc02 > +#define CSR_SSTATUS 0x100 > +#define CSR_SIE 0x104 > +#define CSR_STVEC 0x105 > +#define CSR_SCOUNTEREN 0x106 > +#define CSR_SSCRATCH 0x140 > +#define CSR_SEPC 0x141 > +#define CSR_SCAUSE 0x142 > +#define CSR_STVAL 0x143 > +#define CSR_SIP 0x144 > +#define CSR_SATP 0x180 > +#define CSR_CYCLEH 0xc80 > +#define CSR_TIMEH 0xc81 > +#define CSR_INSTRETH 0xc82 > > -#define xcsr(csr) #csr > +#ifndef __ASSEMBLY__ > > #define csr_swap(csr, val) \ > ({ \ > unsigned long __v = (unsigned long)(val); \ > - __asm__ __volatile__ ("csrrw %0, " xcsr(csr) ", %1" \ > + __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\ > : "=r" (__v) : "rK" (__v) \ > : "memory"); \ > __v; \ > @@ -76,7 +106,7 @@ > #define csr_read(csr) \ > ({ \ > register unsigned long __v; \ > - __asm__ __volatile__ ("csrr %0, " xcsr(csr) \ > + __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \ > : "=r" (__v) : \ > : "memory"); \ > __v; \ > @@ -85,7 +115,7 @@ > #define csr_write(csr, val) \ > ({ \ > unsigned long __v = (unsigned long)(val); \ > - __asm__ __volatile__ ("csrw " xcsr(csr) ", %0" \ > + __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \ > : : "rK" (__v) \ > : "memory"); \ > }) > @@ -93,7 +123,7 @@ > #define csr_read_set(csr, val) \ > ({ \ > unsigned long __v = (unsigned long)(val); \ > - __asm__ __volatile__ ("csrrs %0, " xcsr(csr) ", %1" \ > + __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\ > : "=r" (__v) : "rK" (__v) \ > : "memory"); \ > __v; \ > @@ -102,7 +132,7 @@ > #define csr_set(csr, val) \ > ({ \ > unsigned long __v = (unsigned long)(val); \ > - __asm__ __volatile__ ("csrs " xcsr(csr) ", %0" \ > + __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \ > : : "rK" (__v) \ > : "memory"); \ > }) > @@ -110,7 +140,7 @@ > #define csr_read_clear(csr, val) \ > ({ \ > unsigned long __v = (unsigned long)(val); \ > - __asm__ __volatile__ ("csrrc %0, " xcsr(csr) ", %1" \ > + __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\ > : "=r" (__v) : "rK" (__v) \ > : "memory"); \ > __v; \ > @@ -119,7 +149,7 @@ > #define csr_clear(csr, val) \ > ({ \ > unsigned long __v = (unsigned long)(val); \ > - __asm__ __volatile__ ("csrc " xcsr(csr) ", %0" \ > + __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \ > : : "rK" (__v) \ > : "memory"); \ > }) > -- > 2.7.4 > > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot
LGTM as well. Reviewed-by: Anup Patel <anup.pa...@wdc.com> Regards, Anup _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot