This patch converts the TPC70 to use driver model and device tree
description in both SPL and u-boot proper.

Notable changes (DM/DTS conversion):

- PINCTRL{_IMX6}
- DM_I2C
- enable 'regulator' and 'pmic' commands
- DM_MMC and BLK (USDHC)
- DM_ETH
- DM WDT (including SYSRESET)

Signed-off-by: Lukasz Majewski <lu...@denx.de>

---

 arch/arm/mach-imx/mx6/Kconfig             |  10 ++
 board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c     | 165 +-----------------------------
 board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c | 133 +-----------------------
 configs/kp_imx6q_tpc_defconfig            |  34 +++++-
 include/configs/kp_imx6q_tpc.h            |  21 ----
 5 files changed, 49 insertions(+), 314 deletions(-)

diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index fe5991e7c6..910f82664e 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -485,9 +485,19 @@ config TARGET_KP_IMX6Q_TPC
        select BOARD_EARLY_INIT_F
        select BOARD_LATE_INIT
        select DM
+       select SPL_DM if SPL
        select DM_THERMAL
+       select DM_MMC
+       select DM_ETH
+       select DM_REGULATOR
+       select SPL_DM_REGULATOR if SPL
+       select DM_SERIAL
+       select DM_I2C
+       select DM_GPIO
+       select DM_USB
        select MX6QDL
        select SUPPORT_SPL
+       select SPL_SEPARATE_BSS if SPL
        imply CMD_DM
        imply CMD_SPL
 
diff --git a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c 
b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c
index 97af6bd65b..e819127220 100644
--- a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c
+++ b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c
@@ -9,64 +9,17 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
 #include <asm/arch/mx6-pins.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
 #include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/mxc_i2c.h>
 #include <errno.h>
-#include <fsl_esdhc_imx.h>
-#include <fuse.h>
-#include <i2c.h>
 #include <miiphy.h>
-#include <mmc.h>
-#include <net.h>
-#include <netdev.h>
 #include <usb.h>
 #include <usb/ehci-ci.h>
 #include <led.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define ENET_PAD_CTRL                                                  \
-       (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |  \
-        PAD_CTL_HYS)
-
-#define I2C_PAD_CTRL                                                   \
-       (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |  \
-       PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-#define PC                     MUX_PAD_CTRL(I2C_PAD_CTRL)
-
-static struct i2c_pads_info kp_imx6q_tpc_i2c_pad_info0 = {
-       .scl = {
-               .i2c_mode  = MX6Q_PAD_CSI0_DAT9__I2C1_SCL | PC,
-               .gpio_mode = MX6Q_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
-               .gp = IMX_GPIO_NR(5, 27)
-       },
-       .sda = {
-                .i2c_mode = MX6Q_PAD_CSI0_DAT8__I2C1_SDA | PC,
-                .gpio_mode = MX6Q_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
-                .gp = IMX_GPIO_NR(5, 26)
-       }
-};
-
-static struct i2c_pads_info kp_imx6q_tpc_i2c_pad_info1 = {
-       .scl = {
-               .i2c_mode  = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
-               .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
-               .gp = IMX_GPIO_NR(4, 12)
-       },
-       .sda = {
-                .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
-                .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
-                .gp = IMX_GPIO_NR(4, 13)
-       }
-};
-
 int dram_init(void)
 {
        gd->ram_size = imx_ddr_size();
@@ -83,37 +36,6 @@ int overwrite_console(void)
 }
 
 #ifdef CONFIG_FEC_MXC
-static iomux_v3_cfg_t const enet_pads[] = {
-       IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-       IOMUX_PADS(PAD_ENET_MDC__ENET_MDC       | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-       IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-       IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-       IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-       IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-       IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-       IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
-                  MUX_PAD_CTRL(ENET_PAD_CTRL)),
-       IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-       IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-       IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-       IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-       IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-       IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-       IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
-                  MUX_PAD_CTRL(ENET_PAD_CTRL)),
-       /* AR8031 PHY Reset */
-       IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25  | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static void eth_phy_reset(void)
-{
-       /* Reset AR8031 PHY */
-       gpio_direction_output(IMX_GPIO_NR(1, 25), 0);
-       mdelay(10);
-       gpio_set_value(IMX_GPIO_NR(1, 25), 1);
-       udelay(100);
-}
-
 static int setup_fec_clock(void)
 {
        struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
@@ -125,15 +47,6 @@ static int setup_fec_clock(void)
        return enable_fec_anatop_clock(0, ENET_50MHZ);
 }
 
-int board_eth_init(bd_t *bis)
-{
-       SETUP_IOMUX_PADS(enet_pads);
-       setup_fec_clock();
-       eth_phy_reset();
-
-       return cpu_eth_init(bis);
-}
-
 static int ar8031_phy_fixup(struct phy_device *phydev)
 {
        unsigned short val;
@@ -168,53 +81,6 @@ int board_phy_config(struct phy_device *phydev)
 }
 #endif
 
-#ifdef CONFIG_FSL_ESDHC_IMX
-
-#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
-static struct fsl_esdhc_cfg usdhc_cfg[] = {
-       { USDHC2_BASE_ADDR },
-       { USDHC4_BASE_ADDR },
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-       struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-
-       switch (cfg->esdhc_base) {
-       case USDHC2_BASE_ADDR:
-               return !gpio_get_value(USDHC2_CD_GPIO);
-       case USDHC4_BASE_ADDR:
-               return 1; /* eMMC/uSDHC4 is always present */
-       }
-
-       return 0;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-       int i, ret;
-
-       /*
-        * According to the board_mmc_init() the following map is done:
-        * (U-Boot device node)    (Physical Port)
-        * mmc0                    micro SD
-        * mmc2                    eMMC
-        */
-       gpio_direction_input(USDHC2_CD_GPIO);
-
-       usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-       usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
-
-       for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
-               ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
-               if (ret)
-                       return ret;
-       }
-
-       return 0;
-}
-#endif
-
 #ifdef CONFIG_USB_EHCI_MX6
 static void setup_usb(void)
 {
@@ -224,30 +90,6 @@ static void setup_usb(void)
         */
        imx_iomux_set_gpr_register(1, 13, 1, 0);
 }
-
-int board_usb_phy_mode(int port)
-{
-       if (port == 1)
-               return USB_INIT_HOST;
-       else
-               return USB_INIT_DEVICE;
-}
-
-int board_ehci_power(int port, int on)
-{
-       switch (port) {
-       case 0:
-               break;
-       case 1:
-               gpio_direction_output(IMX_GPIO_NR(3, 31), !!on);
-               break;
-       default:
-               printf("MXC USB port %d not yet supported\n", port);
-               return -EINVAL;
-       }
-
-       return 0;
-}
 #endif
 
 int board_early_init_f(void)
@@ -256,6 +98,10 @@ int board_early_init_f(void)
        setup_usb();
 #endif
 
+#ifdef CONFIG_FEC_MXC
+       setup_fec_clock();
+#endif
+
        return 0;
 }
 
@@ -269,9 +115,6 @@ int board_init(void)
        /* Enable eim_slow clocks */
        setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
 
-       setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &kp_imx6q_tpc_i2c_pad_info0);
-       setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &kp_imx6q_tpc_i2c_pad_info1);
-
        return 0;
 }
 
diff --git a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c 
b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
index e48a577f79..25a5e4b9ba 100644
--- a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
+++ b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
@@ -9,30 +9,12 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
 #include <asm/arch/mx6-ddr.h>
-#include <asm/arch/mx6-pins.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/mxc_i2c.h>
 #include <asm/io.h>
 #include <errno.h>
-#include <fuse.h>
-#include <fsl_esdhc_imx.h>
-#include <i2c.h>
-#include <mmc.h>
 #include <spl.h>
 
-#define UART_PAD_CTRL                                                  \
-       (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |  \
-        PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL                                                 \
-       (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |   \
-        PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
 DECLARE_GLOBAL_DATA_PTR;
 
 static void ccgr_init(void)
@@ -48,60 +30,6 @@ static void ccgr_init(void)
        writel(0x000003FF, &ccm->CCGR6);
 }
 
-/* onboard microSD */
-static iomux_v3_cfg_t const usdhc2_pads[] = {
-       IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-       IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-       IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-       IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-       IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-       IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-       IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16    | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-/* eMMC */
-static iomux_v3_cfg_t const usdhc4_pads[] = {
-       IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-       IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-       IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-       IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-       IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-       IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-       IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-       IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-       IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-       IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-};
-
-/* SD */
-static void setup_iomux_sd(void)
-{
-       SETUP_IOMUX_PADS(usdhc2_pads);
-       SETUP_IOMUX_PADS(usdhc4_pads);
-}
-
-/* UART */
-static iomux_v3_cfg_t const uart1_pads[] = {
-       IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA  | MUX_PAD_CTRL(UART_PAD_CTRL)),
-       IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA  | MUX_PAD_CTRL(UART_PAD_CTRL)),
-};
-
-static void setup_iomux_uart(void)
-{
-       SETUP_IOMUX_PADS(uart1_pads);
-}
-
-/* USB */
-static iomux_v3_cfg_t const usb_pads[] = {
-       IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID       | MUX_PAD_CTRL(NO_PAD_CTRL)),
-       IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31      | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static void setup_iomux_usb(void)
-{
-       SETUP_IOMUX_PADS(usb_pads);
-}
-
 /* DDR3 */
 static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
        .dram_sdclk_0 = 0x00000030,
@@ -255,59 +183,6 @@ static void spl_dram_init(void)
 #endif
 }
 
-struct fsl_esdhc_cfg usdhc_cfg[] = {
-       {USDHC2_BASE_ADDR},
-       {USDHC4_BASE_ADDR},
-};
-
-#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
-int board_mmc_getcd(struct mmc *mmc)
-{
-       struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-       int ret = 0;
-
-       switch (cfg->esdhc_base) {
-       case USDHC2_BASE_ADDR:
-               ret = !gpio_get_value(USDHC2_CD_GPIO);
-               break;
-       case USDHC4_BASE_ADDR:
-               ret = 1; /* eMMC/uSDHC4 is always present */
-               break;
-       }
-
-       return ret;
-}
-
-int board_mmc_init(bd_t *bd)
-{
-       struct src *psrc = (struct src *)SRC_BASE_ADDR;
-       unsigned int reg = readl(&psrc->sbmr1) >> 11;
-       /*
-        * Upon reading BOOT_CFG register the following map is done:
-        * Bit 11 and 12 of BOOT_CFG register can determine the current
-        * mmc port
-        * 0x1                  SD1
-        * 0x3                  SD4
-        */
-
-       switch (reg & 0x3) {
-       case 0x1:
-               SETUP_IOMUX_PADS(usdhc2_pads);
-               usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
-               usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-               gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
-               break;
-       case 0x3:
-               SETUP_IOMUX_PADS(usdhc4_pads);
-               usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
-               usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
-               gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
-               break;
-       }
-
-       return fsl_esdhc_initialize(bd, &usdhc_cfg[0]);
-}
-
 void board_boot_order(u32 *spl_boot_list)
 {
        u32 boot_device = spl_boot_device();
@@ -339,9 +214,8 @@ void board_init_f(ulong dummy)
        /* setup GP timer */
        timer_init();
 
-       setup_iomux_sd();
-       setup_iomux_uart();
-       setup_iomux_usb();
+       /* Early - pre reloc - driver model setup */
+       spl_early_init();
 
        /* UART clocks enabled and gd valid - init serial console */
        preloader_console_init();
@@ -351,7 +225,4 @@ void board_init_f(ulong dummy)
 
        /* Clear the BSS. */
        memset(__bss_start, 0, __bss_end - __bss_start);
-
-       /* load/boot image from boot device */
-       board_init_r(NULL, 0);
 }
diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig
index 87b25e6e1d..abf957f158 100644
--- a/configs/kp_imx6q_tpc_defconfig
+++ b/configs/kp_imx6q_tpc_defconfig
@@ -4,21 +4,28 @@ CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2200
 CONFIG_MX6_DDRCAL=y
 CONFIG_TARGET_KP_IMX6Q_TPC=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
 CONFIG_DISTRO_DEFAULTS=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x400
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
+CONFIG_SD_BOOT=y
 CONFIG_BOOTDELAY=3
 # CONFIG_USE_BOOTCOMMAND is not set
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_SPL_TEXT_BASE=0x00908000
 CONFIG_SPL_RAW_IMAGE_SUPPORT=y
+# CONFIG_TPL_BANNER_PRINT is not set
+CONFIG_SPL_PAYLOAD="u-boot.img"
+CONFIG_SPL_POWER_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR="."
@@ -27,19 +34,44 @@ CONFIG_AUTOBOOT_STOP_STR="."
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+# CONFIG_CMD_PINMUX is not set
 CONFIG_CMD_USB=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_ISO_PARTITION is not set
 # CONFIG_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-kp"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks 
assigned-clock-rates assigned-clock-parents interrupts clocks dmas dma-names"
 CONFIG_ENV_IS_IN_MMC=y
+# CONFIG_BLOCK_CACHE is not set
+CONFIG_SPL_CLK_IMX6Q=y
+CONFIG_CLK_IMX6Q=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_FEC_MXC=y
 CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+# CONFIG_TPL_SERIAL_PRESENT is not set
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
 CONFIG_IMX_WATCHDOG=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h
index 2d1d1203b5..c4dbbf3886 100644
--- a/include/configs/kp_imx6q_tpc.h
+++ b/include/configs/kp_imx6q_tpc.h
@@ -25,32 +25,11 @@
 #define CONFIG_SYS_MALLOC_LEN          (4 * SZ_1M)
 
 /* FEC ethernet */
-#define IMX_FEC_BASE                   ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE            RGMII
-#define CONFIG_ETHPRIME                        "FEC"
-#define CONFIG_FEC_MXC_PHYADDR         0
 #define CONFIG_ARP_TIMEOUT             200UL
 
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_SPEED           100000
-
-/* MMC Configs */
-#define CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR      0
-#define CONFIG_SYS_FSL_USDHC_NUM       2
 #define CONFIG_SYS_MMC_ENV_DEV         1 /* 0 = SDHC2, 1 = SDHC4 (eMMC) */
 #define CONFIG_SUPPORT_EMMC_BOOT
 
-/* UART */
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE           UART1_BASE
-#define CONFIG_CONS_INDEX              1
-#define CONFIG_BAUDRATE                        115200
-
 /* USB Configs */
 #ifdef CONFIG_CMD_USB
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-- 
2.11.0

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