Update DDR configuration with the latest update: - Change DQSGE to 1 for DDR3, to cure missing DQS preamble.
Signed-off-by: Nicolas Le Bayon <nicolas.le.ba...@st.com> Signed-off-by: Patrick Delaunay <patrick.delau...@st.com> --- arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi | 4 ++-- arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi | 5 ++--- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi index dc30360..11e8f2b 100644 --- a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi +++ b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi @@ -16,7 +16,7 @@ * address mapping : RBC * Tc > + 85C : N */ -#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.44" +#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.45" #define DDR_MEM_SPEED 533000 #define DDR_MEM_SIZE 0x20000000 @@ -89,7 +89,7 @@ #define DDR_PTR2 0x042DA068 #define DDR_ACIOCR 0x10400812 #define DDR_DXCCR 0x00000C40 -#define DDR_DSGCR 0xF200001F +#define DDR_DSGCR 0xF200011F #define DDR_DCR 0x0000000B #define DDR_DTPR0 0x38D488D0 #define DDR_DTPR1 0x098B00D8 diff --git a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi index 8158a56..4b70b60 100644 --- a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi +++ b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi @@ -16,8 +16,7 @@ * address mapping : RBC * Tc > + 85C : N */ - -#define DDR_MEM_NAME "DDR3-1066/888 bin G 2x4Gb 533MHz v1.44" +#define DDR_MEM_NAME "DDR3-1066/888 bin G 2x4Gb 533MHz v1.45" #define DDR_MEM_SPEED 533000 #define DDR_MEM_SIZE 0x40000000 @@ -90,7 +89,7 @@ #define DDR_PTR2 0x042DA068 #define DDR_ACIOCR 0x10400812 #define DDR_DXCCR 0x00000C40 -#define DDR_DSGCR 0xF200001F +#define DDR_DSGCR 0xF200011F #define DDR_DCR 0x0000000B #define DDR_DTPR0 0x38D488D0 #define DDR_DTPR1 0x098B00D8 -- 2.7.4 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot